Samsung S5PC100, Руководство пользователя

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Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-8
7) Wake-up time in this case means the time to power-up a power domain.
8) until ARM reset is released
9) until ARM clock is supplied, 300us for APLL locking time
10) until ARM reset is released. If top domain on, wakeup time is XXTI 926 cycles added by APLL locking time (300us). If top
domain off, wakeup time is XXTI 1688 cycles.
11) 5ms for regulator on + XXTI 138 cycles for ARM reset release. 5ms (regulator on-time) can be changed according
to the type of regulator or PMIC (power management IC).
12) until ARM clock is supplied, 1ms for oscillator stabilization time + 300 us for APLL locking time
13) until ARM reset is released. If top domain on, wakeup time is XXTI 896 cycles added by APLL locking time (300us) and
oscillator stabilization time (1ms). If top domain off, wakeup time is XXTI 1688 cycles added by oscillator stabilization time
(1ms).
In SLEEP mode, power for all domains except ALIVE domain is not supplied since external power source is off by
regulator or PMIC, and all PLLs and unnecessary oscillators are disabled. Static power consumption is very small
in SLEEP mode. The only leakage power source is due to power supplied to ALIVE domain.
In STOP and SLEEP mode, PLL is disabled by hardware and OSCs are selectively disabled by setting OSC_EN
field of STOP_CFG and SLEEP_CFG register in PMU.
3.2 NORMAL MODE
In NORMAL mode, clock off, power off, and frequency scaling are used for power saving.
Clock off is done in module-by-module basis. Disable the clock of one or more modules by setting the
corresponding bits in the clock on/off control registers (CLK_GATE_D0_0-2, CLK_GATE_D1_0-5, and
CLK_GATE_SCLK_0-1) in the Clock Controller module.
Frequency scaling is done in PLL-by-PLL basis. Lower the operating frequency of the modules by changing the
PLL P/M/S values. Changing a P/M/S value causes PLL lock operation which takes time 300us. S5PC100 stops
its operation during the PLL lock period since the PLL output clock is masked. Refer to Chapter 2.3 Clock Strategy
to know how to change P/M/S value, and related clock divider value.
Power off is done in block-by-block basis. You can do power off one or more blocks by setting the corresponding
bits in NORMAL_CFG register. The IP blocks which are power-off in NORMAL mode are, MFC, G3D, LCD sub-
system, and TV sub-system (Refer to Table 2.4-2).
The power domain can also be powered on by setting the corresponding bit in NORMAL_CFG register. You can
power on or power-off multiple power domains at the same time by changing multiple bits in the NORMAL_CFG
registers. You should not initiate power on (or power off) before power off (or power on) is finished.