Samsung S5PC100, Руководство пользователя

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MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0)
8.11-10
8 REGISTER DESCRIPTION
Register Address R/W Description Reset Value
MSBM
0xED50_0000 ~
0xED50_3FFC
R/W MODEM I/F SRAM Buffer Memory (AP side) -
Register Address R/W Description Reset Value
INT2AP 0xED50_8000 R/W Interrupt Request to AP Register 0x00003FFE
INT2MSM 0xED50_8004 R/W Interrupt Request to MSM Modem Register 0x00003FFC
MIFCON 0xED50_8008 R/W Modem Interface Control Register 0x00000008
MIFPCON 0xED50_800C R/W Modem Interface Port Control register 0x00000000
MSMINTCLR 0xED50_8010 W MSM Modem Interface Pending Interrupt
Request Clear -
DMA_TX_ADR 0xED50_8014 R/W DMA TX Request Address Register 0x17FE_13FE
DMA_RX_ADR 0xED50_8018 R/W DMA RX Request Address Register 0x1FFE_1BFE
8.1 INTERRUPT REQUEST TO AP REGISTER (INT2AP, R/W, ADDRESS = 0XED50_8000)
INT2AP Bit Description Reset Value
Reserved [31:14] Reserved 0
INT2AP_ADR [13:0] Modem interface requests the interrupt to AP if modem chip
writes this address. This interrupt is cleared by the interrupt
controller of AP and write access to the MSMINTCLR register.
0x3FFE
8.2 INTERRUPT REQUEST TO MODEM REGISTER (INT2MSM, R/W, ADDRESS = 0XED50_8004)
INT2MSM Bit Description Reset Value
Reserved [31:14] Reserved 0
INT2MSM_ADR [13:0] Modem interface (in this module) requests the interrupt to modem
chip if AP writes this address and clears the interrupt if modem
chip write 1 to the corresponding bit field. 0x3FFC
NOTE: It is recommended that AP writes data with half-word access on the interrupt port because AP overwrites the data
in INT2AP if there are INT2AP and INT2MSM sharing the same word.