Samsung S5PC100, Руководство пользователя

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UART S5PC100 USER’S MANUAL (REV1.0)
8.1-18
6.4 UART TX/RX STATUS REGISTER
•
UTRSTAT0, R, Address = 0xEC00_0010
•
UTRSTAT1, R, Address = 0xEC00_0410
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UTRSTAT2, R, Address = 0xEC00_0810
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UTRSTAT3, R, Address = 0xEC00_0C10
There are four UART Tx/Rx status registers namely UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in the
UART block.
UTRSTATn Bit Description Reset Value
Transmitter empty [2] This bit is automatically set to 1 if the transmit buffer register has
no valid data to transmit, and the transmit shift register is empty.
0 = Not empty
1 = Transmitter (transmit buffer & shifter register) empty 1
Transmit buffer
empty [1] This bit is automatically set to 1 if transmit buffer register is empty.
0 = Buffer register is not empty
1 = Buffer register is empty
(In Non-FIFO mode, Interrupt or DMA is requested.
In FIFO mode, Interrupt or DMA is requested, if Tx
FIFO Trigger Level is set to 00 (Empty))
If UART uses FIFO, check Tx FIFO Count bits and Tx FIFO Full bit
in UFSTAT register instead of this bit.
1
Receive buffer
data ready [0] This bit is automatically set to 1 if receive buffer register contains
valid data, received over the RXDn port.
0 = Buffer register is empty
1 = Buffer register has a received data
(In Non-FIFO mode, Interrupt or DMA is requested)
If UART uses the FIFO, check Rx FIFO Count bits and Rx FIFO
Full bit in UFSTAT register instead of this bit.
0