Samsung S5PC100, Руководство пользователя

Страница: 654 / 1863

I
2
C-BUS INTERFACE S5PC100 USER’S MANUAL (REV1.0)
8.2-2
PCLK
Address Register
SDA 4-bit Prescaler
I2C-Bus Control Logic
I2CSTAT I2CCON
Comparator
Shift Register
Shift Register
(I2CDS)
Data Bus
SCL
Figure 8.2-1 I
2
C-Bus Block Diagram
1.1 I
2
C-BUS INTERFACE
The S5PC100 I
2
C-bus interface has four operation modes:
•
Master Transmitter Mode
•
Master Receive Mode
•
Slave Transmitter Mode
•
Slave Receive Mode
Functional relationships among these operating modes are described below.
1.2 START AND STOP CONDITIONS
If the I
2
C-bus interface is inactive, it is usually in Slave mode. In other words, the interface should be in Slave
mode before detecting a Start condition on the SDA line (a Start condition is initiated with a High-to-Low transition
of the SDA line while the clock signal of SCL is High). If the interface state is changed to Master mode, a data
transfer on the SDA line can be initiated and SCL signal generated.
A Start condition transfers one-byte serial data over the SDA line, and a Stop condition terminates the data
transfer. A Stop condition is a Low-to-High transition of the SDA line while SCL is High. The master generates
Start and Stop conditions. The I
2
C-bus gets busy if a Start condition is generated. A Stop condition frees the I
2
C-
bus.
If a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of
address field consists of a 7-bit address and a 1-bit transfer direction indicator (Showing write or read).
If bit 8 is 0, it indicates a write operation (Transmit Operation); if bit 8 is 1, it indicates a request for data read
(Receive Operation).
The master transmits Stop condition to complete the transfer operation. If the master wants to continue the data
transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the
read-write operation is performed in various formats.