Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG
8.10-43
HOST MODE REGISTERS
These registers affect the operation of the core in the Host mode. Host mode registers must not be accessed in
Device mode, as the results are undefined. Host Mode registers are categorized as follows:
•
Host Global registers
•
Host Port Control and Status registers
•
Host Channel-Specific registers
8.2.20 Host Configuration Register (HCFG, R/W, Address = 0xED20_0400)
This register configures the core after power-on. Do not make changes to this register after initializing the host.
HCFG Bit Description R/W Reset Value
Reserved [31:3] - 29'h0040000
FSLSSupp [2] FS- and LS- Only Support
The application uses this bit to control the core's enumeration
speed. Using this bit, the application makes the core enumerate
as a FS host, even if the connected device supports HS traffic.
Do not make changes to this field after initial programming.
•
1'b0 : HS/FS/LS, based on the maximum speed supported by
the connected device
•
1'b1 : FS/LS -only, even if the connected device can support
HS
R/W 1'b0
FSLSPclkSel [1:0] FS/ LS PHY Clock Select
If the core is in FS Host mode
•
2'b00 : PHY clock is 30/60 MHz
•
2'b01 : PHY clock is 48 MHz
•
Others : Reserved
If the core is in LS Host mode
•
2'b00 : PHY clock is 30/60 MHz
•
2'b01 : PHY clock is 48 MHz
•
2'b10 : PHY clock is 6 MHz
•
2'b11 : Reserved
R/W 2'b0