Samsung S5PC100, Руководство пользователя

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CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
2.3-4
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XXTI and XXTO use wide-range OSC pads.
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XusbXTI and XusbXTO use wide-range OSC pads.
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XXTI27 and XXTO27 use wide-range OSC pads.
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XrtcXTI and XrtcXTO use OSC pads for RTC.
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ARMCLK means clock for Cortex A8.
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HCLKD0 means clock for D0_BUS and D0_BUS-attached modules.
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PCLKD0 means clock for APB modules at D0 domain.
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HCLKD1 means clock for D1_BUS and D1_BUS-attached modules.
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PCLKD1 means clock for APB modules at D1 domain.
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HCLKD2 means clock for D2_BUS and D2_BUS-attached modules.
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PCLKD2 means clock for APB modules at D2 domain.
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SCLK_HDMI means clock to HDMI, and MIXER.
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SCLK_48M means 48MHz clock to SPI, MMC, USB HOST1.1 and IrDA.
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SCLK_27M means 27MHz clock to MIXER, MIPI D-PHY, SPI, and MMC.
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SCLK_54M means 54MHz clock to VDAC, TV, MIXER, LCD, and FIMC.
2.2 CLOCKS FROM CMU
CMU generates internal clocks with a various intermediate frequencies using clocks from the clock pads (i.e.,
XXTI, XXTI27, XrtcXTI, and XusbXTI), four PLLs (i.e., APLL, MPLL, EPLL, and HPLL), and USB_OTG PHY clock.
Some of them are selected, pre-scaled, and provided to the corresponding modules. Products of AP typically use
12MHz as an input clock source of APLL, MPLL and EPLL. Samsung recommend 27MHz for input clock of HPLL.
The following components are used to generate internal clocks:
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APLL uses SRCLK as input to generate 50MHz ~ 2GHz
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MPLL uses SRCLK as input to generate 10MHz ~ 600MHz.
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EPLL uses SRCLK as input to generate 10MHz~ 600MHz. This is mainly used for audio clock.
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HPLL uses OSC27_IN as input to generate 10MHz ~ 600MHz clock, especially, this PLL must generate clean
clock for making 74.176MHz and 74.25MHz (HDMI clocks).
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Clock Doubler uses OSC27_IN to generate 54 MHz clock for SD TV out.
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USB OTG PHY uses XusbXTI to generate 30 and 48MHz.