Samsung S5PC100, Руководство пользователя

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INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0)
2.5-12
3 IEM IMPLEMENTATION AND DRIVER SETTING
3.1 DEFINITION OF PERFORMANCE
The maximum frequency of APLL is 1.6GHz. The expected frequency range of ARM Core is from 166MHz to
800MHz. AXI_D0 bus, which is connected to ARM Core, works at 166MHz.
In S5PC100X, CMU only uses clock divider to change performance. If you want to use PLL clock change, you
should change PLL setting for that. With this specification, we should consider about number of the frequency
levels as well as the resolution of each frequency level.
There are divider values for ARM Core clock, AXI_D0 bus AXI clock and HPM clock when PLL output is 1600MHz
in table below.
Table 2.5- 1 Example Divider Values for 1600MHz PLL Output
PLL
Output
(MHz)
ARM Core
Clock
Frequency
(MHz)
HPM Clock
Frequency
(MHz)
AXI Bus
Clock
Frequency
(MHz)
ARM
Clock
Ratio
(f
PLL
/f
ARM
)
HPM
Clock
Ratio
(f
ARM
/f
HPM
)
AXI Bus
Clock
Ratio
(f
PLL
/f
AXI
)
Performance
mapping
(%)
800.0 100.0 2 100.0
533.3 66.7 3 66.7
400.0 50.0 4 50.0
320.0 40.0 5 40.0
266.7 33.3 6 33.3
228.6 28.6 7 28.6
200.0 25.0 8 25.0
177.8 22.2 9 22.2
1600
160.0 20.0
160.0
10
8 10
20.0
There are divider values for ARM Core clock, AXI_D0 bus AXI clock and HPM clock when PLL output is 833MHz
in table below.
Table 2.5- 2 Example Divider Values for 833MHz PLL Output
PLL
Output
(MHz)
ARM Core
Clock
Frequency
(MHz)
HPM Clock
Frequency
(MHz)
AXI Bus
Clock
Frequency
(MHz)
ARM
Clock
Ratio
(f
PLL
/f
ARM
)
HPM
Clock
Ratio
(f
ARM
/f
HPM
)
AXI Bus
Clock Ratio
(f
PLL
/f
AXI
)
Performance
mapping
(%)
833.0 104.1 2 100.0
416.5 52.1 3 50.0
277.7 34.7 4 33.3
208.3 26.0 5 25.0
833
166.6 20.8
166.6
6
8 5
20.0
If you want to add more performance level above 50%, you should put PLL change scheme to CMU.