Samsung S5PC100, Руководство пользователя

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CF CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.5-38
5.2.10 ATA Software Reset (ATA_SWRST, R/W, Address = 0xE780_190C)
ATA_SWRST Bit Description R/W Reset Value
Reserved [31:1] Reserved R
0x0
ata_swrst [0]
Software reset for the ATAPI host
0 = No reset
1 = Resets device registers and all registers of ATAPI
host controller except CPU interface registers.
After software reset, to continue transfer, user must
configure all registers of host controller and device
registers.
R/W
0x0
5.2.11 ATA Interrupt Register (ATA_IRQ, R/W, Address = 0xE780_1910)
ATA_IRQ Bit Description R/W Reset Value
Reserved [31:10] Reserved R
0x0
ebi_abort_rd_int [9]
When ATAPI is aborted by EBI-BACKOFF signal, in
case of read transfer (UDMA/MDMA class). CPU clears
this interrupt by writing “1”.
R/W
0x0
ebi_abort_wr_int [8]
When ATAPI is aborted by EBI-BACKOFF signal, in
case of write transfer (UDMA/MDMA class). CPU clears
this interrupt by writing “1”.
R/W
0x0
ebi_bf_rd_int [7]
When EBI-BACKOFF signal is issued by EBI, In case of
read transfer. If CFCON release the EBI BUS, this bit
clears automatically.
R/W
0x0
ebi_bf_wr_int [6]
When EBI-BACKOFF signal is issued by EBI, in case of
write transfer. If CFCON release the EBI BUS, this bit
clears automatically.
R/W
0x0
mdma_hold_int [5]
If ATAPI device makes pending in MDMA class. CPU
clears this interrupt by writing “1”.
R/W
0x0
sbuf_empty_int [4]
If source buffer is empty.
CPU clears this interrupt by writing “1”.
R/W
0x0
tbuf_full_int [3]
If track buffer is half-full.
CPU clears this interrupt by writing “1”.
R/W
0x0
atadev_irq_int
[2]
If ATAPI device generates interrupt.
CPU clears this interrupt by writing “1”.
R/W
0x0
udma_hold_int
[1]
If ATAPI device makes early termination in UDMA class.
CPU clears this interrupt by writing “1”.
R/W
0x0
xfr_done_int
[0]
If all data transfers are complete.
CPU clears this interrupt by writing “1”.
R/W
0x0