Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER
5.1-13
T0 T1 T2 T3 T4 T5 T6
CK
DQS
DQ
SDRAM command
Q0 Q2 Q3
T7
READ
{Q1, Q0} {Q3, Q2}
{Q1, Q0} {Q3, Q2}
PHY read input FIFO
AXI read channel
RL = 3
RL + rd_fetch = 3
T8
90' phase shifted DQS
Q1
negedge
sampling
negedge
sampling
tDQSCK
+ Delay
Figure 5.1-9 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, low frequency, RL=3, rd_fetch=0)
Delay is relatively small compared to the clock period during low frequencies as shown in Figure 5.1-9.
In this situation, negedge sampling happens before read latency and therefore read fetch is set to zero.
To calculate the LPDDR/LPDDR2 rd_fetch value:
rd_fetch (LPDDR/LPDDR2) = INT((-1 + Delay + 0.5T + 0.25T)/T) = INT(Delay/T - 0.25),
Delay: board delay + PHY input delay, T: clock period, INT(x): the rounded-up integer value of x
Therefore, if the value of Delay/T is less than 0.25, rd_fetch is set to zero