Samsung S5PC100, Руководство пользователя

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ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.3-12
3 I/O DESCRIPTION
Function Signal I/O Description PAD TYPE
OND_DATA[15:0] I/O
Data Bus outputs address during memory read/ write
address phase, inputs data during memory read data
phase and outputs data during memory write data
phase.
Xm0DATA[15:0] muxed
OND_CSn[1:0] O
Chip Selects are activated if the address of a memory is
within the address region of each bank. Xm0CSn[3:2] is
assigned to either SROMC or OneNAND controller by
System Controller SFR setting.
Active LOW.
Xm0CSn[3:2] muxed
OND_WEn O
Write Enable indicates that the current bus cycle is a
write cycle. Active LOW.
Xm0WEn muxed
OND_OEn O
Output Enable indicates that the current bus cycle is a
read cycle. Active LOW.
Xm0OEn muxed
OND_INT[1:0] I
Interrupt inputs from OneNAND memory Bank 0, 1.
If OneNAND memory is not used, these signals should
be tied to zero.
Xm0FRnB[1:0] muxed
OND_AVALID O
Address valid output. In the POP products, address and
data are multiplexed. Xm0ADDRVALID indicate if the
bus is used for address. Active LOW.
Xm0FCLE muxed
OND_PRn O
System reset output for OneNAND memory. Active
LOW.
Xm0FWEn muxed
OND_SMCLK O
Static memory clock for synchronous static memory
devices.
Xm0FALE muxed
NOTE: Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals.