Samsung S5PC100, Руководство пользователя

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INTELLIGENT ENERGY MANAGEMENT S5PC100 USER’S MANUAL (REV1.0)
2.5-4
2 FUNCTIONAL DESCRIPTIONS
To support IEM, S5PC100 includes special IPs as below:
•
Power Management Unit supporting IEM
•
Intelligent Energy Controller
•
Clock Management Unit supporting Dynamic Clock Generation
♦
Clock Management Unit in System Controller acts as Dynamic Clock Generator
•
Advanced Power Controller supporting Dynamic Voltage Control
♦
APC1 acts as Dynamic Voltage Controller
•
The Power Supply Unit supporting Dynamic Voltage Scaling
♦
Power Supply Unit is the only off-chip component.
•
Hardware Performance Monitor
♦
This is optional and only required for a closed loop system
Figure 2.5-2 IEM Block Diagram shows the on-chip IEM components required for a complete solution of IEM and
how they connect together briefly.
2.1 IEM SYSTEM COMPONENTS
2.1.1 Intelligent Energy Controller
The Intelligent Energy Controller (IEC) from ARM is designed for reuse in a wide variety of AMBA based designs
and has a standard APB slave interface for programming the registers. This provides an Applications
Programming Interface (API) for the IEM software. The IEC connects through defined interfaces to SoC-specific
components such as the APC1.
The IEC uses prediction performance level requests from the IEM software. The performance setting is
communicated to the IEC so that the System-on-Chip specific and product platform scaling hardware can be
controlled to bring the system to that performance point. Battery life is extended by lowering the operating
frequency and voltage of SoC components, such as the processor, and consequently reducing energy
consumption.
The IEC provides an abstracted view of the SoC-specific performance scaling hardware. It is responsible for
translating the performance prediction made by the IEM software (0-100% of maximum performance) into an
appropriate performance point at which the system runs and then controlling the scaling hardware to achieve
operation at that target point. This is achieved through passing a target performance request to the CMU and
APC1.
The IEC also measures the work done in the system to ensure that the software deadlines are not going to be
missed. Additionally, the IEC supports a maximum performance hardware request feature. The IEC is designed to
map to an implementation-defined set of index levels. You must configure the IEC to define the CMU frequencies
and APC1 voltage levels that can be selected. These frequencies and voltages depend on the capabilities of the
dynamic or adaptive power supply technology to support multiple operating performance points.
The IEC interfaces to the CMU and APC1 blocks via PMU through a thermometer encoded interface protocol, that
indicates to the IEC the current performance level. This protocol is specified to support interfacing across
asynchronous clock domains between high-speed PLL and clock-generator and low-speed voltage scaling