Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) CAMERA INTERFACE
9.3
-41
8.23 Status Register (CISTATUSn)
y
CISTATUS0, Address = 0xEE20_0064
y
CISTATUS1, Address = 0xEE30_0064
y
CISTATUS2, Address = 0xEE40_0064
CISTATUSn Bit Description
RW
Reset
Value
M L
OvFiY [31] Overflow state of FIFO Y R 0
X X
OvFiCb [30] Overflow state of FIFO Cb R 0
X X
OvFiCr [29] Overflow state of FIFO Cr R 0
X X
VSYNC [28]
Camera VSYNC (CPU refers this bit for first SFR setting
after external camera muxing. It is seen in the ITU-R BT
656 mode)
R 0
X X
FrameCnt [27:26]
Frame count of output DMA. This counter value means
the next frame number
R 0
X X
WinOfstEn [25] Window offset enable status. R 0
X X
FlipMd [24:23] Flip mode of output DMA R 0
X X
ImgCptEn [22] Image capture enable of global camera interface R 0
X X
ImgCptEn_SC [21] Image capture enable of scaler path R 0
X X
VSYNC_A [20]
External camera A VSYNC. Polarity inversion was not
adopted.
R X
X X
VSYNC_B [19]
External camera B VSYNC. Polarity inversion was not
adopted.
R X
X X
OvRLB [18] Overflow status of Line Buffer for Rotation. R 0
X X
FrameEnd [17]
When frame operation finish, FrameEnd is generated.
and FrameEnd is clear by user setting ‘ 0’
R/W 0
X X
LastCaptureEnd [16]
Last frame capture status. LastCaptureEnd is clear by
user setting ‘ 0’ . This singnal is applied only
Camera input mode.
R/W 0
X X
VVALID_A [15] External camera A VVALID R X
X X
VVALID_B [14] External camera B VVALID R X
X X
IRQ_CAM [13] Interrupt Status for Camera Input Mode R 0
X X
IRQ_DMAend [12] Interrupt Status for DMA Frame End for DMA Input Mode R 0
X X
FrameCptStatus [11]
Capture frame control status.
1 = Present capture enable , 0 = Present capture disable
R 0
X X
FrameFieldStatu
s
[10]
ITU CAMERA field status. Internal value after inverse
polarity.
1 = Present frame Field1 , 0 = Present frame Field0
R 0
X X
Reserved [9:0] Reserved - 0
X X