Samsung S5PC100, Руководство пользователя

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IROM CODE S5PC100 USER’S MANUAL (REV1.0)
2.6-2
The boot loader is divided into the BL0(1st boot loader) and the BL1(2nd boot loader).
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BL0 which is placed in iROM loads BL1 from the booting device to iRAM. The booting device is determined by
the OM and NFMOD pins. In addition, according to the secure boot key values, BL0 checks the integrity of
BL1.
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BL1 should initializes the DRAM controller. After initializing the DRAM controller, it loads the OS image from
the booting device to DRAM. And, according to the secure boot key values, BL1 checks the integrity of the OS
image.
The operation on the booting time is presented in Figure 2.6-1.
2 FUNCTIONAL DESCRIPTION
2.1 RESET STATUS
There are several scenarios for system reset such as hardware reset, watchdog reset, software reset, and wake
up from power down modes. For each scenario, the ‘must’ functions are summarized as Table 2.6-1.
Table 2.6-1 Functions on BL0
PLL on BL1 loading
Reset (XnRESET, Watchdog, Software) O O
Wakeup from ESLEEP O O
Wakeup from SLEEP O O
Wakeup from DEEP_STOP (Top-domain on) X X
Wakeup from DEEP_STOP (Top-domain off with retention) X X
Wakeup from DEEP_STOP (Top-domain off) O O
Wakeup from DEEP_IDLE (Top-domain on)
X X
Wakeup from DEEP_IDLE (Top-domain off with retention) X X
Wakeup from DEEP_IDLE (Top-domain off) O O
On Hardware reset and watchdog reset, the system has to do full booting including BL1 and OS image loading.
On ESLEEP case, the set product does not ensure that DRAM memory’s contents are preserved. So, full booting
is also required. These reset status which requires full booting is classified as reset group0.
Because SLEEP mode is different from ESLEEP in that DRAM memory’s contents are preserved, it does not
need an OS image loading to DRAM. However, SoC internal power is not supplied during SLEEP mode, all
contents in internal SRAM is not preserved. So, BL1 should be loaded again. This reset status is classified as
reset group1.
On SW reset, the contents of both internal SRAM and external DRAM are preserved. So, any boot loader loading
is not required at all. Although the top block’s power is gated in DEEP_STOP and DEEP_IDLE mode, If the
internal SRAM is retention so that boot loader re-loading is not necessary. But internal SRAM is off then iROM
reload BL1. Wake up from DEEP_STOP and wake up from DEEP_IDLE statuses are classified as reset group2.
When system enters into all power down modes except ESLEEP, current system status should be saved to safe
memory region such as DRAM so that the system continues processing seamlessly after waking up from power