Samsung S5PC100, Руководство пользователя

Страница: 225 / 1863

Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-26
The behavior of EPLL in the other power down modes, is the same as the other PLLs (APLL, MPLL, HPLL).
The initial-state of S5PC100 after wake-up from the SLEEP mode is almost the same as the Power-On-Reset
state except for the contents of the external DRAM is preserved.
On the other hand, S5PC100 automatically recovers the previous working state after wake-up from the STOP
mode, and DEEP-STOP (top domain on).
Finally, after wake-up from the DEEP-IDLE (top domain off), DEEP-STOP (top domain off) and SLEEP mode, s/w
should recover the previous working state by using preserved information.
Table 2.4-9 Status of PLLs and ARMCLK/HCLK after Wake-Up
Mode before wake-up
APLL/MPLL/HPLL
on/off after wake up
EPLL on/off after
wakeup
HCLK after wakeup
IDLE unchanged unchanged PLL Output
DEEP-IDLE
(Top domain on)
unchanged unchanged PLL Output
DEEP-IDLE
(Top domain off)
off
→
off unchanged PLL reference clock
STOP
off
→
on (by H/W) off
→
on (by H/W)
PLL Output
DEEP-STOP
(Top domain on)
off
→
on (by H/W) off
→
on (by H/W) PLL Output
DEEP-STOP
(Top domain off)
off
→
off off
→
off PLL reference clock
SLEEP off
→
off off
→
off PLL reference clock
6.7 DAC
DAC has two power modes: Run and Power-down mode
•
In Run mode, DAC sends and receives data normally.
•
In Power-down mode, all power to DAC is off internally.
In NORMAL mode, both power modes can be used.
If DAC is in use, then it is in Run mode.
If DAC is not in use, it enters into Power-down mode to save static power by setting register in TVOUT logic.
In IDLE mode and DEEP-IDLE mode (top domain on), DAC keeps its operation or power state in NORMAL.
Before it enters to DEEP-IDLE mode (top domain off), STOP and DEEP-STOP, it is recommended that DAC
enters into Power-down mode.
Before it enters to SLEEP mode, power to DAC should be off to prevent leakage current.