Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) I2S CONTROLLER(5.1CH)
10.2-5
5 AUDIO SERIAL DATA FORMAT
5.1 I2S-BUS FORMAT
The I2S bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select
clock I2SLRCLK, and serial bit clock I2SBCLK; the device generating I2SLRCLK and I2SBCLK is the master.
Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the
LSB depends on the word length. The transmitter sends the MSB of the next word at one clock period after the
I2SLRCLK is changed. Serial data sent by the transmitter is synchronized with either the trailing or the leading
edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the
serial clock signal, and therefore there are some restrictions to transmit data that is synchronized with the leading
edge.
The LR channel select line indicates the channel being transmitted. I2SLRCLK is changed either on a trailing or
leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is latched on the
leading edge of the clock signal. The I2SLRCLK line changes one clock period before the MSB is transmitted.
This allows the slave transmitter to derive synchronous timing of the serial data that is set up for transmission.
Furthermore, it enables the receiver to store the previous word and clears the input for the next word.
5.2 MSB (LEFT) JUSTIFIED
MSB-Justified (Left-Justified) format is similar to I2S bus format, except that in MSB-justified format, the
transmitter always sends the MSB of the next word at the same time whenever the I2SLRCLK is changed.
5.3 LSB (RIGHT) JUSTIFIED
LSB-Justified (Right-Justified) format is opposite to the MSB-justified format. In other word, the transferring serial
data is aligned with ending point of I2SLRCLK transition.
Figure 10.2-5 shows the audio serial format of I2S, MSB-justified, and LSB-justified. Note that in this figure, the
word length is 16-bit and I2SLRCLK makes transition every 24 cycle of I2SBCLK (BFS is 48 fs, where fs is
sampling frequency; I2SLRCLK frequency).