Samsung S5PC100, Руководство пользователя

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USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -60
8.2.35 Device Status Register (DSTS, R, Address = 0xED20_0808)
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from
Device ALL Interrupts (DAINT) register.
DSTS Bit Description R/W Reset
Value
Reserved [31:22] - 10'h0
SOFFN [21:8] Frame or Microframe Number of the Received SOF
If the core is operating at high speed; this field contains a
microframe number. If the core is operating at full or low speed,
this field contains a frame number.
R 14'h0
Reserved [7:4] - 4'h0
ErrticErr [3] Erratic Error
The core sets this bit to report any erratic errors seen on the
UTMI+. Due to erratic errors, the OTG core goes into Suspended
state and an interrupt is generated to the application with Early
Suspend bit of the Core Interrupt register. If the early suspend is
asserted due to an erratic error, the application performs a soft
disconnect recover. R 1'b0
EnumSpd [2:1] Enumerated Speed
Indicates the speed at which the OTG core has come up after
speed detection through a chirp sequence.
•
2'b00: High speed (PHY clock is 30 MHz or 60 MHz)
•
2'b01: Full speed (PHY clock is 30 MHz or 60 MHz)
•
2'b10: Low speed (PHY clock is 6 MHz).
•
2'b11: Full speed (PHY clock is 48 MHz).
Low speed is not supported for devices using a UTMI+ PHY.
R 2'b01
SuspSts [0] Suspend Status
In device mode, this bit is set as long as a Suspend condition is
detected on the USB. The core enters the Suspended state if
there is no activity on the line_state signal for an extended period
of time. The core comes out of the suspend:
•
If there is any activity on the line_state signal
•
If the application writes to the Remote Wakeup Signaling bit in
the Device Control register.
R 1'b0