Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) IRDA
8.4-15
6.6 IRDA LINE STATUS REGISTER(IRDA_LSR, R, ADDRESS = 0XEC60_0014)
IrDA_LSR Bit Description Initial State
Tx Empty [7] Transmitter empty. This bit is set to '1' if TX FIFO is empty and the
transmitter front-end is idle. 1
Reserved [6] - 0
Received Last
Byte from Rx
FIFO [5] Last byte received from RX FIFO. It is set to a '1' if the
microcontroller reads the last byte of a frame from the RX FIFO
and cleared if the MCU reads the IrDA_LSR register. 0
Frame Length
Error [4] Frame length error. It is set to '1' if a frame exceeding the
maximum frame length predefined by IrDA_RXFLL and
IrDA_RXFLH register is received. This bit is cleared if the
microcontroller reads the IrDA_LSR register. If this error is
detected, current frame reception is terminated. Data receiving is
stopped until the next BOF is detected. Bit 4 is cleared to '0' if the
IrDA_LSR register is read by the microcontroller. 0
PHY Error [3] PHY error. In FIR mode, It is set to a '1' if an illegal 4PPM symbol
is received. In IrDA_MIR mode, if an abort pattern (more than 7
consecutive '1's) is received during reception, this bit is set to '1'. It
is cleared if microcontroller reads the LSR register. 0
CRC Error [2] CRC error. Bit 2 is set to '1' if a bad IrDA_CRC is detected on data
receive. It is cleared to '0' if microcontroller reads the LSR register. 0
Reserved [1] - 1
Rx FIFO Empty [0] RX FIFO empty. It indicates that the RX FIFO is empty. If the state
of RX FIFO turns into empty, it is set to '1'. If the RX FIFO is not
empty, it is set to '0'. 1