Samsung S5PC100, Руководство пользователя

Страница: 155 / 1863

S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER
2.3-5
In typical S5PC100 applications:
•
APLL is used for Cortex A8 and D0_BUS domain (i.e., ARMCLK, HCLKD0, PCLKD0, HCLKD0_SECSS, and
SCLK_ONENAND).
•
MPLL is used for D1_BUS domain clock (HCLKD1 and PCLKD1) and other peripheral clocks (i.e., audio IPs,
SPI, and etc.).
•
EPLL is used for peripheral clocks (i.e., audio IPs, SPI, and etc.).
•
HPLL is mainly used for a HD video clock (i.e., SCLK_HDMI).
Clock controller allows the bypassing of PLLs for slow clock and the connection/ disconnection of the clock to
each block (clock gating) by software, which results in power reduction.
3 CLOCK RELATIONSHIP
Clocks have the following relationship:
•
D0 bus domain
♦
freq(APLLCLK) = n x freq(ARMCLK), where n = 2 ~ 8, 10, 12, 14, 16
−
Two cascaded divider = DIV_APLL (divide up-to 2) & DIV_ARM (divide up-to 8)
♦
freq(ARMCLK) = n x freq(HCLKD0), where n = 1 ~ 8
♦
freq(PCLKD0) = freq(HCLKD0) / n, where n = 1 ~ 8
♦
freq(HCLKD0_SECSS) = freq(HCLKD0) / n, where n = 1 ~ 8
♦
freq(SCLK_ONENAND) = freq(HCLKD0) / n, where n = 1 ~ 4 (sync with D0 bus mode)
♦
freq(SCLK_ONENAND2) = freq(ONENANDCLK) / 2 (sync with D0 bus mode)
•
D1 bus domain
♦
freq(PCLKD1) = freq(HCLKD1) / n, where n = 1 ~ 8
•
D2 bus domain
♦
HCLKD2 and PCLKD2 have no relationship.
The following values are for the high-performance operation:
•
freq(ARMCLK) = 667 MHz
•
freq(HCLKD0) = 166 MHz
•
freq(PCLKD0) = 83 MHz
•
freq(HCLKSECSS) = 83 MHz
•
freq(ONENANDCLK) = 166 MHz (sync mode), 133 MHz (async mode)
•
freq(ONENANDCLK_2) = 83 MHz (sync mode), 66.5MHz (async mode)
•
freq(HCLKD1) = 133 MHz
•
freq(PCLKD1) = 66.5 MHz
•
freq(HCLKD2) = 83 MHz
•
freq(PCLKD2) = 66 MHz