ASYNC BRIDGE
S5PC100 USER’S MANUAL (REV1.0)
3.4-6
T1
Data is written into the FIFO.
T2
The write pointer update occurs.
T3
The first synchronization stage of this value to the read side occurs because enough time has elapsed
since the write pointer updated.
T4
The second synchronization stage occurs and enables synchronized pointer visible to the read side.
T5
The read side asserts its valid signal because it has compared the read and synchronized write pointers
and they are different.
T6
The data is read.
T7
The read pointer update occurs. The old or new value being captured is unpredictable because this
value is changing on the ACLKS edge, when the synchronizer is sampling. In this case the old value is
captured.
T8
The read pointer starts synchronizing to the write side.
T9
Synchronization is complete.
After T9
The read side can again indicate that it is ready to accept data.
1.3.2 Gray Code
The Gray code used for an N-entry FIFO has 2N values in its sequence, and the order of the values is chosen so
that each value, when XORed with the value N places away from it, gives the same result and does not give that
result when XORed with any other value in the sequence. This enables the fullness and emptiness to be
determined by comparing the two counters:
•
Emptiness is shown by the read and write counters being the same.
•
Fullness is shown by the result of XORing the read and write counters being the first value in the second half
of the sequence, at position N.
The required Gray code can be calculated by an algorithm:
•
The number of bits required in the Gray code, k, can be calculated as:
k = ceil(log2(N)) +1
Where ceil represents a function that rounds its argument up to the nearest integer.
•
The first N values, positions 0 to N-1 in the sequence, are derived from the binary value of their position in the
sequence: Bits of the binary value B[k-1:0] is mapped to the bits of Gray coded value G[k-1:0] using the
following rules:
G[k-1] = B[k-1] (== 0)
G[i] = B[i] XOR B[i+1]
where
0<=i<k-1
Содержание S5PC100
Страница 1: ...USER S MANUAL S5PC100 June 2009 REV 1 01 Copyright 2009 Samsung Electronics Inc All Rights Reserved ...
Страница 13: ...PRODUCT OVERVIEW S5PC100 USER S MANUAL REV1 0 1 1 10 16 level alpha blending ITU BT601 656 format output ...
Страница 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Страница 33: ...BALL MAP SIZE POP S5PC100 USER S MANUAL REV1 0 1 1 8 VSS_HPLL AA12 VSSQ_UOTG AA19 VSS_UOTG AF21 VSS_ADC Y24 ...
Страница 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Страница 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Страница 159: ...S5PC100 USER S MANUAL REV1 0 CLOCK CONTROLLER 2 3 9 Figure 2 3 3 S5PC100 Clock Generation Circuit1 ...
Страница 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Страница 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Страница 328: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 10 Figure 3 2 6 Structure of the Coresight DAP Components ...
Страница 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Страница 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Страница 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Страница 524: ...S5PC100 USER S MANUAL REV1 0 CF CONTROLLER 5 5 29 48 DO9 Data 9 CF_D 9 49 D10 Data 10 CF_D 10 50 GND Ground ...
Страница 545: ...EXTERNAL BUS INTERFACE S5PC100 USER S MANUAL REV1 0 5 6 2 3 BLOCK DIAGRAM Figure 5 6 1 Memory Interface Through EBI ...
Страница 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Страница 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Страница 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Страница 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Страница 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Страница 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Страница 926: ...MODEM INTERFACE S5PC100 USER S MANUAL REV1 0 8 11 4 4 ADDRESS MAPPING Figure 8 11 2 MODEM I F Address Mapping ...
Страница 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Страница 1019: ...S5PC100 USER S MANUAL REV1 0 DISPLAY CONTROLLER 9 1 5 Figure 9 1 2 Block Diagram of the Data Flow ...
Страница 1110: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 2 3 1 ORIGINAL IMAGE 3 2 FLIP VERTICAL 3 3 FLIP HORIZONTAL ...
Страница 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Страница 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Страница 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Страница 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Страница 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Страница 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Страница 1310: ...S5PC100 USER S MANUAL REV1 0 3D ACCELERATOR 9 6 83 Figure 9 6 18 Per Fragment Function Block Diagram ...
Страница 1321: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 94 Interface with AXI Bus FIMG_3DSEV1 1 AXI DMA support AMBA AXI BUS protocol ...
Страница 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Страница 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Страница 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Страница 1584: ...MFC MULTI FORMAT CODEC S5PC100 USER S MANUAL REV1 0 9 11 16 5 2 ENCODING FLOW Figure 9 11 11 Encoding Flow ...
Страница 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Страница 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Страница 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Страница 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Страница 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Страница 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Страница 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...
Страница 1841: ...S5PC100 USER S MANUAL REV1 0 ELECTRICAL DATA 12 1 9 EXTCLK tRESW nRESET Figure 12 1 4 Manual Reset Input Timing ...
Страница 1846: ...ELECTRICAL DATA S5PC100 USER S MANUAL REV1 0 12 1 14 6 ONENAND AC ELECTRICAL CHARACTERISTICS Figure 12 1 7 OneNand Flash Timing ...