Samsung S5PC100, Руководство пользователя

Страница: 443 / 1863

ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.3-6
2.5 ADDRESS MAPPING
There are four kinds of interfaces supported by the controller. These interfaces are selected through the value of
bits 27 and 26 of the incoming address. The interface mapping determines the way how the lower 26 bits of the
address bus are used.
addr[27:26] Interface Description
00 MAP00 Boot read or buffer read/Write during RMW operations.
01 MAP01 Array read/write
10 MAP10 Commands
11 MAP11 Direct access
2.5.1 MAP00
The MAP00 interface are used to communicate with either of the dataram buffers or the boot buffer. This is
considered an “execute in place” (XIP) buffer, which means that the selection of the buffer is invisible to the
command requestor. The starting address for the buffer always be 0x0, and the maximum address is based on the
BOOT_BUF_SIZE register (for normal operation) or the DATA_BUF_SIZE register (for read/modify/write
operations.)
The value of the address bits [16:0] (addr[0] should be zero) is the address of the buffer.
If the controller is initialized, the controller accesses the read-only section of flash memory of boot code. This code
is read and used to configure for the specific memory device.
During normal operation, the XIP buffer points to the boot buffer and the user may only read the data. However, if
following a read/modify/write sequence, the XIP buffer points to the dataram0 buffer and you modify any word of
data through read or write MAP00 commands.
If a MAP00 command is being used and the controller is not in the middle of a read/modify/write sequence, only
AHB read transactions are appropriate. If a MAP00 command is received with an AHB write in this case, an
interrupt is triggered and the command is ignored.
2.5.2 MAP01.
The MAP01 interface is used for block data transfers to and from the memory device to a specific sector of the
flash array. Since the controller only supports page addresses (FSA must be set to 0), an entire page must be
read or written at a time. The actual number of commands used depends on the size of the data to be transferred.
Even if multiple commands are required, the same address should be used until the entire block is transferred.
The write data should be written from the start of the block to the end of the block. If the controller receives the
final word of the transfer, it issues commands necessary to program the data into the array.
The meaning of the address bits [25:0] can be found in Table 5.2-1.
MAP01 command allows the host device to read or write specific pages of the flash memory. Byte enables will be
ignored for writes and reads, and the controller always writes an entire page. The write data must be written from
the start of the page to the end of the page. Once the last word of the page is received, the controller issues the
commands necessary to program the data into the array.
If a read or write command is received during an ongoing erase operation, as long as the read/ write is not to an
address in the erase area, the erase operation will be suspended (if possible) and the read/ write is completed. At
the end of the read/ write, the erase operation resumes. If the device is not able to suspend the erase, or if the