Samsung S5PC100, Руководство пользователя

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Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-4
has retention F/F in top domain keeps the state of F/F if top domain is power-off, but the module that has normal
F/F in top domain loses the state of F/F if the top domain is power-off. If top domain is powered up again, a
wakeup reset is not invoked for the modules that have retention F/F, but a wake up reset is invoked for the
modules that have normal F/F.
The retention modules in TOP domain are listed in Table 2.4-4.
The power-up takes time to stabilize the internal logic gates and memory after power is supplied again. The
power-up time is necessary because a simultaneous power-up of all logic gates and all memories is not allowed
since simultaneous power-up drains a large amount of current and may cause system malfunction.
There are two wakeup techniques in logic part. One technique is applied to TOP domain and the other one is
applied to SUB domains except System Timer domain. Note that System Timer is always ON except SLEEP
mode, since internal switch is not OFF in DEEP-IDLE (top domain off) and DEEP-STOP (top domain off).
First technique:
The logic gates in TOP domain are powered on in two steps, and then memories are powered on one by one
memory group. Two steps means that power to about 10% of all switches are supplied first, and the power of
remaining 90% switches is supplied after some time. This is automatically done by hardware logic. The power-up
time is composed of the logic power-up time and the memory power-up time. These are determined by the
oscillator frequency, the number of memories and the values set in the OSC_FREQ and
INTERNAL_PWR_STABLE registers. The count values vary depending on the size of the logic gates and the
number of memories.
Second technique:
The logic gates and memory in SUB domains except System Timer domain are turned ON at the same time. But
to prevent wakeup noise from occurring, the power to switches is supplied in two steps in similar with first
technique. Power to about 10% switches of all is supplied first, and the power of remaining 90% switched is
supplied after some time goes. This is automatically done by hardware logic. The power-up time is determined by
the oscillator frequency, the number of memories and the values set in the OSC_FREQ and
INTERNAL_PWR_STABLE registers. The count values vary depending on the size of the logic gates and the
number of memories.
External power off means that power to S5PC100 is externally off using regulator or PMIC (Power Management
IC). PMU in S5PC100 generates power control signal to regulator or PMIC. If external power off is applied, the
states of Normal F/F and Retention F/F are lost. Therefore, if you want to save some important data, you should
move those data to external memory, and restore those data when wakeup event occurs.
To reduce the dynamic power consumption, S5PC100 uses clock off and frequency scaling. IP module basis
disables clocks in S5PC100. Reduce the clock frequency if the system is not required to operate at the maximum
frequency.
To reduce power consumption further in the system level, S5PC100 include following features.
•
Make DRAM enter self-refresh mode when S5PC100 enters STOP, DEEP-STOP and SLEEP mode.
To reduce the static current, S5PC100 supports block-based power off. In specific applications, a certain group of
IP modules are not required to run and therefore do not need to be powered on. For example, in case of MP3
playback, Multi-Format Codec (MFC), Video modules (Camera interface, JPEG, Video processor, Mixer, etc.), and
3D graphics core do not need to operate and can be power-off for the minimum static power consumption.
S5PC100 internal modules are grouped into ten power domains based on their functions as shown in Table 2.4-2