Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) 3D-ACCELERATOR
9.6-27
3.4 HOW TO SEND DWORDS FROM CPU TO THE HOST INTERFACE
There is a Host-FIFO in the Host Interface. CPU can transfer only DWORD data to the Host Interface. If CPU
writes more data than the Host-FIFO can actually store, the Host Interface makes HREADY, one of AMBA bus
signals, low. In this case, AMBA bus is granted to 3D-ACCELERATOR and any other IP on the same AMBA bus
can not get a right to use the bus, which is not a desirable situation. The read-only HI_DWSPACE register is used
to ease this situation. HI_DWSPACE holds the number of empty DWORD space in the Host-FIFO. Host-FIFO is
in Host Interface and is able to store upto 32 DWORDs.
Whenever CPU sends the count, indices, or the
geometry data, CPU must get HI_DWSPACE value and transfer DWORDs as much as the value of
HI_DWSPACE.
Generally speaking, HI_DWSPACE does not tell CPU the exact empty space because the clock signals fed into
3D-ACCELERATOR and AMBA bus can be different. (If clock signals are same, HI_DWSPACE has the exact
value.) Hence, HI_DWSPACE is affected by both AMBA bus (writing DWORDs into the Host-FIFO) and the
internal situation (fetching DWORDs from the Host-FIFO).
If the read value of HI_DWSPACE is less than the actual free space in the Host-FIFO, the writing operation ends
without any problem. On the other hand, if the read value of HI_DWSPACE is more than the number of written
DWORDs, the Host Interface makes HREADY signal low and extends the transfer. However, the difference
between the read HI_DWSPACE value and the actual value is usually small.
After CPU reading HI_DWSPACE and transferring DWORDs as much as the read value, CPU can do the other
job or process, or continue to send the other part of the geometry data repeating the same procedure. The CPU
can use the interrupt scheme of 3D-ACCELERATOR. It depends wholy on the device driver.
Interrupts and Vertex Buffer are very useful schemes when a geometry is transferred. (See Section “HOW TO
USE THE VERTEX BUFFER AS A TEMPORAL BUFFER USING INTERRRUPTS” for more information.)
3.5 THE TYPE OF INDEX TRANSFERRED FROM CPU
The IdxType field in HI_CONTROL controls how much index exists in a DWORD from CPU. If IdxType is
unsigned int type, there is only one 32-bit index in a transferred DWORD. In the case of unsigned short type, two
16-bit indices are in a DWORD. In the case of unsigned byte type, four 8-bit indices are available.
The remained indices in a DWORD, when all indices are used, are ignored. For example, if three vertices with
unsigned byte index type are transferred, a DWORD data is used for them. In this case, the last unsigned byte in
the DWORD is ignored.
3.6 DATA TRANSFER TO THE VERTEX BUFFER
Before the contents of the Vertex Buffer are used, the geometry data must be resided in the Vertex Buffer. First,
the 16-byte-aligned destination address in the Vertex Buffer is set to HI_VBADDR. And then, a serise of DWORD
written into HI_VBDATA is stored into the Vertex Buffer (Burst writes are possible). The address in HI_VBADDR is
automatically incremented by 16 (in bytes) whenever 4 DWORDs are written into HI_VBDATA. Therefore, the
destination address does not need to be updated for every DWORD written into HI_VBDATA. Note that the
number of DWORD written into HI_VBDATA must be the multiples of 4. Only when four DWORDs are transferred
from CPU, thoes four DWORDs are stored into the Vertex Buffer. (If 3 DWORDs are transferred, those DWORDs
are not stored into the Vertex Buffer wating another DWORD to be transferred.)