Samsung S5PC100, Руководство пользователя

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PCM AUDIO INTERFACE S5PC100 USER’S MANUAL (REV1.0)
10.5-14
6.7 PCM FIFO STATUS REGISTER
y
PCM_0_FIFO_STAT, R/O, Address = 0xF240_001C
y
PCM_1_FIFO_STAT, R/O, Address = 0xF250_001C
The PCM_n_FIFO_STAT register is used to report FIFO status.
The bit definitions for the PCM_n_IRQ_STATUS Register are described below:
PCM_n_FIFO_STAT Bit Description Reset Value
Reserved [31:20] Reserved 0
TXFIFO_COUNT [19:14] To indicate TXFIFO usage. 0
TXFIFO_EMPTY [13] To indicate whether TXFIFO is empty. 0
TXFIFO_ALMOST_EMPTY [12] To indicate whether TXFIFO is almost empty. 0
TXFIFO_FULL [11] To indicate whether TXFIFO is full. 0
TXFIFO_ALMOST_FULL [10] To indicate whether TXFIFO is almost full. 0
RXFIFO_COUNT [9:4] To indicate RXFIFO usage. 0
RXFIFO_EMPTY [3] To indicate whether RXFIFO is empty. 0
RXFIFO_ALMOST_EMPTY [2] To indicate whether RXFIFO is almost empty. 0
RX_FIFO_FULL [1] To indicate whether RXFIFO is full. 0
RX_FIFO_ALMOST_FULL [0] To indicate whether RXFIFO is almost full. 0
6.8 PCM INTERRUPT CLEAR REGISTER
y
PCM_0_CLRINT, W/O, Address = 0xF240_0020
y
PCM_1_CLRINT, W/O, Address = 0xF250_0020
The PCM_n_CLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing
interrupt asserted. Writing any values on this register clears interrupts for both ARM and DSP. Reading this
register is not allowed. Clearing interrupt must be prior to resolving the interrupt condition, else another interrupt
that would occur after this interrupt may be ignored.
PCM_n_CLRINT Bit Description Reset Value
PCM_CLRINT [31:0] Interrupt is cleared if this bit is written to any value