Samsung S5PC100, Руководство пользователя

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CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
2.3-12
7 DETAILED CLOCK DESCRIPTION
7.1 CPU AND BUS CLOCK
Cortex A8 supports only synchronous mode between CPU and bus (D0 Sync at Figure 2.3-5). D0 and D1 are
asynchronous to each other.
Figure 2.3-5 CPU and Bus Clock
Some clocks can be gated by using SFR.
Table 2.3-6. CPU and Bus Clock
Clock Related SFR
HCLKD0, PCLKD0 CLK_GATE_D0_0, CLK_GATE_D0_1, CLK_GATE_D0_2
HCLKD0_SECSS CLK_GATE_D0_0[5]
SCLK_ONENAND, SCLK_ONENAND2 CLK_GATE_SCLK_0[2]
HCLK CLK_GATE_D1_0, CLK_GATE_D1_1, CLK_GATE_D1_2
PCLK CLK_GATE_D1_3, CLK_GATE_D1_4, CLK_GATE_D1_5
Caution) ARM clock setting
Clock to ARM (ARMCLK) must be divided when using APLL. It means that at least one of the ARM clock dividers
(DIV
APLL
and DIV
ARM
) must be set to more than 1 (Possible ARM clock division value = 2, 3, ~ 8, 10, 12, 14, 16).
As shown in Figure 2.3-5, DIV
APLL
divides up-to 1.334GHz input, DIV
ARM
and DIV
APLL2
divides up-to 667MHz input,
please consider upper-limit of dividers when setting. If PLL clock is more than 667MHz, you cannot use DOUT
AM
path. Use MOUT
MPLL
path for MUX
AM
.