Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER
5.1-33
4.2.11 AC Timing Register for Auto Refresh of memory (TimingAref, R/W, Address=0xE600_0030)
TIMINGAREF Bit Description R/W
Reset
Value
Reserved [31:16] Should be zero 0x0
t_refi [15:0]
Average Periodic Refresh Interval
Should be minimum. memory tREFI (all bank) < t_refi *
T(mclk),
For example, for the all bank refresh period of 7.8us, and an
mclk frequency of 133MHz, the following value should be
programmed :
7.8 us * 133 MHz = 1038
R/W 0x40E
4.2.12 AC Timing Register for the Row of memory (TimingRow, R/W, Address=0xE600_0034)
TIMINGROW Bit Description R/W
Reset
Value
t_rfc [31:24]
Auto refresh to Active / Auto refresh command period, in
cycles
t_rft * T(mclk) should be greater than or equal to the minimum
value of memory tRFC.
R/W 0xF
t_rrd [23:20]
Active bank A to Active bank B delay, in cycles
t_rrd * T(mclk) should be greater than or equal to the minimum
value of memory tRRD.
R/W 0x2
t_rp [19:16]
Precharge command period, in cycles
t_rp * T(mclk) should be greater than or equal to the minimum
value of memory tRP.
R/W 0x3
t_rcd [15:12]
Active to Read or Write delay, in cycles
t_rcd * T(mclk) should be greater than or equal to the minimum
value of memory tRCD
R/W 0x3
t_rc [11:6]
Active to Active period, in cycles
t_rc * T(mclk) should be greater than or equal to the minimum
value of memory tRC.
R/W 0xA
t_ras [5:0]
Active to Precharge command period, in cycles
t_ras * T(mclk) should be greater than or equal to the minimum
value of memory tRAS.
R/W 0x6