Samsung S5PC100, Руководство пользователя

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SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.12-38
PRNSTS Bit Description Reset Value
WTTRANACT [8] Write Transfer Active (ROC)
This status indicates that a write transfer is active. If this bit is 0, it
means no valid write data exists in the Host Controller.
This bit is set in either of the following cases:
(1) After the end bit of the write command.
(2) If 1 is written to Continue Request in the
Block Gap Control
register to restart a write transfer.
This bit is cleared in either of the following cases:
(1) After getting the CRC status of the last data block as specified by
the transfer count (Single and Multiple)
(2) After getting the CRC status of any block where data transmission
is about to be stopped by a Stop At Block Gap Request.
During a write transaction, if this bit is changed to 0 a Block Gap
Event interrupt is generated, as result of the Stop At Block Gap
Request being set. This status is useful for the Host Driver to
determine the right time to issue commands during write busy.
1 = Transferring data
0 = No valid data
0
Reserved
[7:3]
Reserved
0
DATLINEACT [2] DAT Line Active (ROC)
This bit indicates whether one of the DAT line on SD Bus is in use.
(a) In the case of read transactions
This status indicates if a read transfer is executing on the SD Bus.
Change in this value from 1 to 0 between data blocks generates a
Block Gap Event interrupt in the
Normal Interrupt Status register.
This bit is set in either of the following cases:
(1) After the end bit of the read command.
(2) If 1 is written to Continue Request in the Block Gap Control
register to restart a read transfer.
This bit is cleared in either of the following cases:
(1) If the end bit of the last data block is sent from the SD Bus to the
Host Controller.
(2) When beginning a wait read transfer at a stop at the block gap
initiated by a Stop At Block Gap Request.
The Host Controller waits at the next block gap by driving Read Wait
at the start of the interrupt cycle. If the Read Wait signal is already
driven (data buffer cannot receive data), the Host Controller waits for
current block gap by continuing to drive the Read Wait signal. It is
necessary to support Read Wait in order to use suspend/ resume
function.
(b) In the case of write transactions
This status indicates that a write transfer is executing on the SD Bus.
Change in this value from 1 to 0 generates a Transfer Complete
interrupt in the
Normal Interrupt Status register.
0