Samsung S5PC100, Руководство пользователя

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BALL MAP & SIZE (POP) S5PC100 USER’S MANUAL (REV1.0)
1.1-2
1.2 PIN NUMBER ORDER
Table 1.3-1 S5PC100 580 FCFBGA Pin Assignment
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Pin Number Order (1/4)
Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name
A1 VSS B14 Xm0ADDR[4] C27 XpwmTOUT[2] F16 Xm0ADDR[0]
A2 VSS B15 Xm0CFOEn D1 Xm0WEn F17 Xmmc0DATA[2]
A3 Xm0DATA[1] B16 Xm0ADDR[19] D2 Xm0FALE F18 Xmmc1DATA[3]
A4 Xm0DATA[2] B17 VDDQ_B D3 Xm0DATA[5] F19 XpwmTOUT[1]
A5 VDDQ_B B18 Xm0IORDn D7 Xm0DATA[13] F20 Xmmc0DATA[1]
A6 Xm0DATA[6] B19 XspiCSn[1] D8 Xm0ADDR[11] F21 VDD_ARM
A7 Xm0DATA[10] B20 XjTMS D9 VSS F25 VSS
A8 VDD_DRAM B21 Xi2c0SCL D10 Xm0ADDR[6] F26 XspiCSn[0]
A9 Xm0CSn[2] B22 XpwmTOUT[0] D11 Xm0ADDR[10] F27 Xi2c1SDA
A10 Xm0ADDR[13] B23 Xmmc1DATA[2] D12 Xm0CFWEn G1 VDDQ_B
A11 Xm0FRnB[1] B24 XuRXD[0] D13 Xm0ADDR[8] G2 VDDQ_B
A12 VDDQ_B B25 VDD_DRAM D14 Xm0RESET G3 Xm0OEn
A13 Xm0ADDR[18] B26 VSS D15 VSS G4 XvVD[23]
A14 Xm0REG B27 VSS D16 Xm0DATA_RDn G6 VSS
A15 XefVGATE_0 C1 Xm0FRnB[0] D17 Xmmc0DATA[5] G7 VDDQ_M0
A16 Xm0FREn C2 Xm0FCLE D18 Xmmc0DATA[7] G8 Xm0ADDR[9]
A17 VDDQ_B C3 VSS D19 Xi2c0SDA G9 Xm0FRnB[2]
A18 Xm0INPACKn C4 Xm0DATA[3] D20 Xmmc1DATA[0] G10 Xm0WAITn
A19 N.C C5 Xm0DATA[4] D21 Xmmc1CLK G11 Xm0ADDR[2]
A20 XjTCK C6 Xm0DATA[8] D25 XuTXD[2] G12 VDDQ_DDR
A21 XjTDO C7 Xm0DATA[12] D26 XspiMOSI[0] G13 VDDQ_DDR
A22 XuRXD[2] C8 Xm0DATA[15] D27 XuRXD[1] G14 VSS
A23 XuTXD[1] C9 VSS E1 XvVD[9] G15 VSS
A24 Xmmc0CMD C10 Xm0ADDR[5] E2 Xm0CSn[4] G16 Xm0ADDR[7]
A25 XuRXD[3] C11 Xm0IOWRn E3 Xm0FWEn G17 Xmmc0DATA[3]
A26 VSS C12 Xm0ADDR[16] E25 XuCTSn[0] G18 Xmmc1CDn
A27 VSS C13 Xm0ADDR[20] E26 XjTRSTn G19 Xmmc0DATA[0]
B1 VSS C14 Xm0CDn E27 VDD_DRAM G20 VDD_ARM
B2 VSS C15 VSS F1 XvVD[4] G21 VDD_ARM
B3 Xm0DATA[0] C16 Xm0ADDR[1] F2 XvVD[15] G22 XuRTSn[0]
B4 Xm0DATA[7] C17 XnRESET F3 XvVD[22] G24 XspiCLK[0]
B5 VDDQ_B C18 Xmmc0CLK F7 VDDQ_M0 G25 XDDR2SEL
B6 Xm0DATA[9] C19 XspiMOSI[1] F8 VDD_INT G26 XjTDI
B7 Xm0DATA[11] C20 XspiMISO[1] F9 Xm0ADDR[15] G27 XuCTSn[1]
B8 Xm0DATA[14] C21 VSS F10 Xm0INTRQ H1 XvVD[3]
B9 Xm0BEn[0] C22 Xmmc0DATA[6] F11 Xm0FRnB[3] H2 XvVD[8]
B10 Xm0IORDY C23 XuTXD[0] F12 Xm0ADDR[14] H3 Xm0CSn[5]
B11 Xm0CSn[3] C24 XuRTSn[1] F13 Xm0ADDR[3] H4 XvVD[1]
B12 VDDQ_B C25 VSS F14 VSS H6 VDDQ_M0
B13 Xm0CSn[1] C26 XuTXD[3] F15 Xm0ADDR[17] H7 Xm0ADDR[12]