Samsung S5PC100, Руководство пользователя

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2D-ACCELERATOR S5PC100 USER’S MANUAL (REV1.0)
6.1 GENERAL REGISTERS
6.1.1 Control Register (CONTROL_REG, W, Address = 0xEE80_ 0000)
CONTROL_REG Bit Description Reset Value
Reserved [31:1] Reserved 0x0
R [0] Software Reset
Write to this bit results in a one-cycle reset signal to
FIMG2D graphics engine. Every command register and
parameter setting register will be assigned the “Reset
Value”, and the command FIFO will be cleared.
0x0
6.1.2 Interrupt Enable Register (INTEN_REG, R/W, Address = 0xEE80_ 0004)
INTEN_REG Bit Description Reset Value
Reserved [31:11] Reserved 0x0
CCF [10] Current Command Finished interrupt enable.
If this bit is set, when the graphics engine finishes the
execution of current command, an interrupt occurs, and
the INTP_CMD_FIN flag in INTC_PEND_REG will be set.
0x0
ACF [9] All Commands Finished interrupt enable.
If this bit is set, when the graphics engine finishes the
execution of all commands in the command FIFO, an
interrupt occurs, and the INTP_ALL_FIN flag in
INTC_PEND_REG will be set.
0x0
FIFO_FULL [8] Command FIFO Full interrupt enable.
If this bit is set, when command FIFO is full (32 entries), an
interrupt occurs, and the INTP_FULL flag in the interrupt
pending register (INTC_PEND_REG) will be set.
0x0
Reserved [7:1] Reserved 0x0
FIFO_INT_E [0] If this bit is set, when the number of entries occupied in
command FIFO is greater or equal to FIFO_INT_LEVEL
(in FIFO_INTC_REG), an interrupt occurs, and the
INTP_FIFO_LEVEL flag in the interrupt pending register
(INTC_PEND_REG) will be set. 0x0
6.1.3 FIFO Interrupt Control Register (FIFO_INTC_REG, R/W, Address = 0xEE80_ 0008)
FIFO_INTC_REG Bit Description Reset Value
Reserved [31:6] Reserved 0x0
FIFO_INT_LEVEL [5:0] If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED
(in FIFO_STAT_REG) is greater or equal to
FIFO_INT_LEVEL, an interrupt occurs. 0x18
9.5-14