Samsung S5PC100, Руководство пользователя

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CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
2.3-28
10 INDIVIDUAL REGISTER DESCRIPTIONS
10.1 PLL CONTROL REGISTERS
S5PC100 has four internal PLLs, which are APLL, MPLL, EPLL, and HPLL. They are controlled by the following
eight special registers.
10.1.1 PLL Lock
•
Control PLL locking period for APLL (APLL_LOCK, R/W, Address = 0xE010_0000)
•
Control PLL locking period for MPLL (MPLL_LOCK, R/W, Address = 0xE010_0004)
•
Control PLL locking period for EPLL (EPLL_LOCK, R/W, Address = 0xE010_0008)
•
Control PLL locking period for HPLL (HPLL_LOCK, R/W, Address = 0xE010_000C)
•
RESERVED (RESERVED, Address = 0xE010_0010 ~ 0xE010_00FC)
A PLL requires locking period if input frequency is changed or frequency division (multiplication) values are
changed. PLL_LOCK register specifies this locking period, which is based on PLL's source clock. During this
period, PLL output will be masked with '0'.
APLL_LOCK /
MPLL_LOCK /
EPLL_LOCK /
HPLL_LOCK
Bit Description Reset Value
Reserved [31:16] Reserved 0x0000
PLL_LOCKTIME [15:0]
Required input clock count needed to generate a stable
PLL output
0xFFFF
NOTE:
Max lock time in A/M/E/HPLL is 300usec. The value of PLL_LOCKTIME is based on input clock count. For
example, when input clock frequency is 12MHz and lock time is 300us, the value of PLL_LOCKTIME will be
3600(=0xE10).