Samsung S5PC100, Руководство пользователя

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PCM AUDIO INTERFACE S5PC100 USER’S MANUAL (REV1.0)
10.5-2
2 PCM AUDIO INTERFACE
The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input
PCMCODEC_CLK that is used to generate the serial shift timing. The PCM interface outputs a serial data out, a
serial shift clock, and a sync signal. Data is received from the external Codec over a serial input line. The serial
data in, serial data out, and sync signal are all synchronized to the serial shift clock.
The serial shift clock, PCMSCLK, is generated from a programmable divide of the input PCMCODEC_CLK. The
sync signal, PCMSYNC, is generated based upon a programmable number of serial clocks and is one serial clock
wide.
The PCM data words are 16-bit wide, serially shifted out 1-bit per PCMSCLK. Only one 16-bit word is shifted out
for each PCMSYNC. The PCMSCLK continues to toggle even after all 16-bit have been shifted out. The
PCMSOUT data will be a undefined after the 16-bit word is complete. The next PCMSYNC signals the start of the
next PCM data word.
The TX FIFO provides the 16-bit data word to be serially shifted out. This data is serially shifted out MSB first, one
bit per PCMSCLK. The rising edge of the PCMSCLK is used to clock out PCM serial output data (PCMSOUT).
The MSB bit position relative to the PCMSYNC is programmable to be either coincident with the PCMSYNC or
one PCMCLK later. After all 16-bit have been shifted out, generation of an interrupt is optional to indicate the end
of the transfer.
At the same time data is being shifted out, the PCMSIN input is used to serially shift data in from the external
codec. The data is received MSB first and is clocked on the falling edge of PCMSCLK. The position of the first bit
is programmable to correspond with the PCMSYNC or one PCMSCLK later.
The first 16-bit are serially shifted into the PCM_DATAIN register which is then loaded into the RX FIFO.
Subsequent bits are ignored until the next PCMSYNC.
Various Interrupts are available to indicate the status of the RX and TX FIFO. Each FIFO has a programmable flag
to indicate if the CPU needs to service the FIFO. For the RX FIFO there is an interrupt which is raised if the FIFO
exceeds a certain programmable almost_full depth. Similarly there is a programmable almost_empty interrupt for
the TX FIFO.
3 PCM TIMING
The following figures show the timing relationship for the PCM transfers. Note in all cases, the PCM shift timing is
derived by dividing the input clock, PCMCODEC_CLK. While the timing is based upon the PCMCODEC_CLK,
there is no attempt to realign the rising edge of the output PCMSCLK with the original PCMCODEC_CLK input
clock. These edges are skewed by internal delay through the pads as well as the divider logic. This does not
represent a problem because the actual shift clock, PCMSCLK, is output with the data. Furthermore, even if the
PCMSCLK output is not used, the skew is significantly less than the period of the PCMCODEC_CLK and should
not represent a problem since most PCM interfaces capture data on the falling edge of the clock.
Figure 10.5-1 shows a PCM transfer with the MSB configured to correspond with the PCMSYNC. This MSB
positioning corresponds to setting the MSB_POS_WR and MSB_POS_RD bits in DSP_PCMCTL register to be
LOW.