Samsung S5PC100, Руководство пользователя

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DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.1-34
4.2.13 AC Timing Register for the Data of memory (TimingData, R/W, Address=0xE600_0038)
TIMINGDATA Bit Description R/W
Reset
Value
t_wtr [31:28]
Internal write to Read command delay, in cycles
t_wtr * T(mclk) should be greater than or equal to the minimum
value of memory tWTR.
t_wtr must be 0x1 in case of JEDEC LPDDR.
R/W 0x1
t_wr [27:24]
Write recovery time, in cycles
t_wr * T(mclk) should be greater than or equal to the minimum
value of memory tWR
R/W 0x2
t_rtp [23:20]
Internal read to Precharge command delay, in cycles
t_rtp * T(mclk) should be greater than or equal to the minimum
value of memory tRTP.
t_rtp must be 0x1 in case of JEDEC LPDDR.
R/W 0x1
cl [19:16]
CAS Latency (for LPDDR/DDR/DDR2), in cycles
cl should be greater than or equal to the minimum value of
memory CL.
R/W 0x3
Reserved [15:12] Should be zero 0x0
wl [11:8]
Write data latency (for only LPDDR2), in cycles
wl should be greater than or equal to the minimum value of
memory WL
R/W 0x2
Reserved [7:4] Should be zero 0x0
rl [3:0]
Read data latency (for only LPDDR2), in cycles
rl should be greater than or equal to the minimum value of
memory RL
R/W 0x4
* tDAL (Auto precharge write re precharge time) = t_wr + t_rp (automatically calculated)