Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER
2.3-29
10.1.2 Control PLL Output Frequency for APLL (APLL_CON, R/W, Address = 0xE010_0100)
PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates
output after PLL locking period. The output frequency of PLL is controlled by the MDIV, PDIV, and SDIV values.
APLL_CON Bit Description Reset Value
ENABLE [31] PLL enable control (0: Disables, 1: Enables) 0
LOCKED [30]
PLL is locked after locking time (locking time is set at
PLL_LOCK SFR)
0
Reserved [29:26] Reserved 0
MDIV [25:16] PLL M divide value 0x190
Reserved [15:14] Reserved 0
PDIV [13:8] PLL P divide value 0x3
Reserved [7:3] Reserved 0
SDIV [2:0] PLL S divide value 0x2
The reset value of APLL_CON generates 400MHz output clock respectively, if the input clock frequency is 12MHz.
NOTE:
The output frequency is calculated by the following equation:
F
OUT
= MDIV X F
IN
/ (PDIV X 2
SDIV
)
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
PDIV: 1
≤
PDIV
≤
63
MDIV: 64
≤
MDIV
≤
1023
SDIV: 0
≤
SDIV
≤
5
F
ref
(=F
IN
/ PDIV): 3MHz
≤
F
ref
≤
6MHz
F
VCO
(=MDIV X F
IN
/ PDIV): 1000MHz
≤
F
VCO
≤
2000MHz
F
OUT
: 50MHz
≤
F
VCO
≤
2000MHz
Ex) For FOUT=500MHz, P=3, M=500, S=2