Samsung S5PC100, Руководство пользователя

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DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.1-2
1.2 BLOCK DIAGRAM
Control
Queue
(8/16
entries )
Read Data
FIFO
(32 depth)
Write Data
Buffer
(32 depth)
Queue
Arbiter
Bank FSM information
S0
S1 S2
Bank0
FSM
Latency Control
Timing & configuration information
AXI
Slave
Interface
Bus Interface Block
Scheduler Block
APB
Interface
Functional
Registers
Low Power
Manager
64bit
AXI Channel
32bit APB3
AXI Low Power
Channel
PHY
I/F
SEC
DDR
PHY
DLL
AREF
Cmd
Final
Arbiter
Direct
Cmd
Data
Control
Memory Interface Block
32 bit DDR / DDR 2 /
LPDDR / LPDDR 2
Figure 5.1-1 Overall Block Diagram
Figure 5.1-1 shows the overall block diagram of the controller. The block diagram shows the bus interface block,
scheduler block, and memory interface block, which connects and interfaces with the SEC DDR PHY.
The bus interface block saves the bus transactions for memory access that come from the AXI slave port to the
command queue. Additionally it saves the write data to the write buffer or sends the read data to the Master via
the AXI bus. It also acts as a read FIFO if AXI Master is not ready and has an APB interface for special function
registers/ direct commands and an AXI low power channel interface.
The Scheduler block uses the memory bank Finite State Machine (FSM) information to arbitrate the bus
transactions in the command queues and transforms the commands into a memory command type, which is sent
to the Memory interface block. It also controls the write and read data flow between the memory and the AXI bus.
The Memory interface block updates each memory bank state according to the memory command coming from
the scheduler and sends the bank state back to the scheduler. It creates a memory command depending on the
memory latency and sends the command to the SEC DDR PHY via the PHY interface.