Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) Power Management
2.4-73
12 IEM CLOCK CHANGE SCHEME
In this section, we describe how to change HPM and ARM clocks if you want to change IEM performance.
IEM supports eight performance levels. It depends on system and application how many performance levels you
use.
To implement clock change scheme, PMU in S5PC100 has 22 registers (6 registers for IEM configurations, 8
registers for PLL P/M/S value, and 8 register for clock dividers). Among 22 registers, 9 registers for IEM
configurations are common to all performance levels, and two registers (one for PLL P/M/S value, the other for
clock divider) are assigned to each performance level. (See Table 2.4-58)
Additionally, there are three registers for special clock management, namely, FREQ_CPU, FREQ_DPM, and
DVSEMCLK_EN. The detailed descriptions are given in next section.
Table 2.4-58 Registers for IEM Clock Change
Performance Level IEM configuration PLL P/M/S value Clock Divider value
8 level APLL_CON_L8 CLKDIV_IEM_L8
7 level APLL_CON_L7 CLKDIV_IEM_L7
6 level APLL_CON_L6 CLKDIV_IEM_L6
5 level APLL_CON_L5 CLKDIV_IEM_L5
4 level APLL_CON_L4 CLKDIV_IEM_L4
3 level APLL_CON_L3 CLKDIV_IEM_L3
2 level APLL_CON_L2 CLKDIV_IEM_L2
1 level
DCGIDX_MAP0
DCGIDX_MAP1
DCGIDX_MAP2
DCGPERF_MAP0
DCGPERF_MAP1
DVCIDX_MAP
APLL_CON_L1 CLKDIV_IEM_L1
In stage of chip initialization, the above registers are set to defined values.
If we want to change IEM performance, we need to set only new target performance level to IEM_ IEC register,
then the appropriate value corresponding to target performance level are used to change current target level.
0 Performance level is defined to clock stopped state, so if you change IEM performance level to 0 level, you
should use IDLE mode of PMU, and WFI mode of Cortex-A8.