Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) Power Management
2.4-33
7.2 HARDWARE RESET
Hardware reset is asserted if the XnRESET pin is driven to low, and all units in the system (except RTC function
module) are reset to known states.
During the hardware reset, the following actions occur:
•
All internal registers and Cortex-A8 go into their pre-defined reset state.
•
All pins get their reset state, and XnBATF pin is ignored.
•
The XnRSTOUT pin is asserted when XnRESET is driven.
Hardware reset is asserted when an external source drives the XnRESET input pin low. XnRESET is non-
maskable, and therefore is always applicable. Upon assertion of XnRESET, S5PC100 enters into reset state
regardless of the previous state. For hardware reset to be asserted actually, XnRESET must be held long enough
to allow internal stabilization and propagation of the reset state.
Table 2.4-14 lists up pin names that should be supplied during reset.
Table 2.4-14 List of Power Pin Names supplied during reset
Power Pin Names supplied during reset
VDD_MCP, VDDQ_DDR, VDD_MO, VDDQ_LCD, VDDQ_CI, VDDQ_MMC, VDDQ_AUD, VDDQ_MSM,
VDDQ_SYS0, VDDQ_SYS2, VDDQ_SYS5, VDDQ_CAN, VDDQ_EXT, VDDQ_UH, VDDINT, VDD_ALIVE,
VDD_ARM, VDD_ADC
Manual reset input timing for hareware reset is shown in Figure 2.4-6.
EXTCLK means XXTI input (XOM[0]=0) or XusbXTI input (XOM[0]=1). Refer to Table 2.4-13 for
t
RESW
parameter.
Figure 2.4- 6 Manual Reset Input Timing