Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG
8.10-27
8.2.8 OTG USB Configuration Register (GUSBCFG, R/W, Address = 0xED20_000C)
This register configures the core after power-on or a changing to Host mode or Device mode. It contains USB and
USB-PHY related configuration parameters. The application must program this register before starting any
transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
GUSBCFG Bit Description R/W Reset
Value
Reserved [31:16] - 16'h0
PHY Low-
Power Clock
Select [15] PHY Low-Power Clock Select
Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
FS and LS modes, the PHY usually operate on a 48-MHz clock
to save power.
•
1'b0 : 480-MHz Internal PLL clock
•
1'b1 : 48-MHz External clock
* Note: This bit must be configured with
OPHYPWR.pll_powerdown.
1'b0
Reserved [14:10] - 5'h5
HNPCap [9] HNP
−
Capable
The application uses this bit to control the OTG cores's HNP
capabilities.
•
1'b0 : HNP capability is not enabled
•
1'b1 : HNP capability is enabled
R/W 1'b0
SRPCap [8] SRP
−
Capable
The application uses this bit to control the OTG core's SRP
capabilities.
•
1'b0 : SRP capability is not enabled
•
1'b1 : SRP capability is enabled
R/W 1'b0
Reserved [7:4] - 4'h0
PHYIf [3] PHY Interface
The application uses this bit to configure the core to support a
UTMI+ PHY with an 8- or 16-bit interface.
Only 16-bit interface is supported. This bit must be set to 1.
•
1'b0 : 8 bits
•
1'b1 : 16 bits
R/W 1'b0
TOutCal [2:0] HS/ FS Timeout Calibration
Set this bit to 3'h7.
R/W 3'h0