Samsung S5PC100, Руководство пользователя

Страница: 1063 / 1863

S5PC100 USER’S MANUAL (REV1.0) DISPLAY CONTROLLER
9.1-49
6.2 VIDEO MAIN CONTROL 1 REGISTER (VIDCON1, R/W, ADDRESS = 0XEE00_ 0004)
VIDCON1 Bit Description Reset Value
LINECNT
(read only) [26:16] Provide the status of the line counter (read only)
Up count from 0 to LINEVAL 0
FSTATUS [15] Field Status (read only).
0 = ODD Field 1 = EVEN Field 0
VSTATUS [14:13] Vertical Status (read only).
00 = VSYNC 01 = BACK Porch
10 = ACTIVE 11 = FRONT Porch 0
Reserved [12:8] Reserved
IVCLK [7] This bit controls the polarity of the VCLK active edge.
0 = Video data is fetched at VCLK falling edge
1 = Video data is fetched at VCLK rising edge 0
IHSYNC [6] This bit indicates the HSYNC pulse polarity.
0 = Normal 1 = Inverted 0
IVSYNC [5] This bit indicates the VSYNC pulse polarity.
0 = Normal 1 = Inverted 0
IVDEN [4] This bit indicates the VDEN signal polarity.
0 = Normal 1 = Inverted 0
Reserved [3:0] Reserved 0x0
6.3 VIDEO MAIN CONTROL 2 REGISTER (VIDCON2, R/W, ADDRESS = 0XEE00_ 0008)
VIDCON2 Bit Description Reset Value
Reserved [31:24] Reserved 0
EN601 [23] Control ITU601 output enable
0 = Disables 1 = Enables
0
EN656 [22] Control ITU656 output enable.
0 = Disables 1 = Enables 0
Reserved [21:15] Reserved 0
Reserved [14] Reserved
Note :This bit should be 1
0
TVFORMATSEL [13:12] This bit indicates output format of YUV data.
00 = RGB 01 = YUV422
1x = YUV444
0
Reserved [11:9] Reserved 0
OrgYCbCr [8] This bit indicates order of YUV data.
0 = Y - CbCr 1 = CbCr – Y 0
YUVOrd [7] This bit indicates order of Chroma data.
0 = Cb - Cr 1 = Cr – Cb 0
Reserved [6:0] Reserved 0