Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) USB HOST CONTROLLER
8.9-25
Table 8.9-10 UHCCONCURRED Bit Definitions
UHCCONCURRE
D
Bit Description R/W Reset Value
CCED [31:4] ControlCurrent Enpoint Descriptor
This pointer advances to the next ED after serving the
present one. The UHC continues processing the list
from where it left off in the last frame. If it reaches the
end of the Control list, the UHC checks the
ControlListFilled bit of in HcCommandStatus
(UHCCOMS[CLF]). If set, it copies the content of
HcControlHeadED (the UHCCHED register) to the
UHC Control Current ED (this register) and clears the
UHCCOMS[CLF] bit. If UHCCOMS[CLF] is not set, the
UHC does nothing. The HCD is allowed to modify this
register if the ControlListEnable bit of HcControl
(UHCHCON[CLE]) is cleared. If UHCHCON[CLE] is
set, the HCD only reads the instantaneous value of
this register. Initially, this is set to zero to indicate the
end of the Control list. This pointer/address is 32-byte
aligned, therefore, the lower 4 bits are always 0. R/W
- [3:0] Fixed at 0 R
5.2.11 USB HcBulkHeadED Register (UHCBHDED, Address = 0xED40_0028)
The UHCBHDED register contains the physical address of the first Endpoint Descriptor of the Bulk list. The
register organization and individual bit definitions are shown in Table 8.9-12. The lower 4 bits are read as 0 and
are unaffected by Writes.
Table 8.9-11 UHCBHDED Bit Definitions
UHCBHDED Bit Description R/W Reset Value
BHED [31:4] BulkHead Endpoint Descriptor
The UHC traverses the Bulk list starting with the
HcBulkHeadED pointer (UHCBHED register, Refer to
Section 20.8.11); the content is loaded from the HCCA
during the initialization of the UHC. This pointer/address is
32 byte aligned, therefore, the lower 4 bits are always 0.
R/W
- [3:0] Fixed at 0 R