Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) INTELLIGENT ENERGY MANAGEMENT
2.5-7
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supports the closed-loop AVS voltage control in conjunction with the HPM
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voltage table to support the open-loop DVS
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supports thermometer-encoded interface for a target performance level request and a current performance
level update
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parameterized design supports up to eight performance levels
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sleep mode (retention level) power-down support
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revision identification register for porting software driver compliance
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DFT-ready for SCAN-based ATPG.
The APC1 receives the required target performance request from the IEC via PMU. This performance request is
then translated to a voltage level that is communicated to the PSU through an interface such as the. The PWI has
been developed jointly by ARM and National Semiconductor to provide a high-speed, low-power control interface
between an IEM-enabled SoC and an external power supply unit.
For an open loop system, the APC1 can either:
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wait a programmed time that is dependent on the response time of the PSU, before signaling to the CMU that
the target performance can be achieved
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interrogate the PSU through the PWI for a VDD_OK signal indication.
If the PSU provides intermediate stable voltage level indication, then the APC1 can also determine this through
the PWI.
2.1.3 Hardware Performance Monitor
The Hardware Performance Monitor (HPM) is designed for reuse and easy implementation. Although it is a
separate entity in physical partition, the HPM is an integral part of the APC1 for an AVS power management
system. The HPM is not a memory mapped device. An HPM is required for closed loop control, but not for an
open loop control system.
The HPM tracks the system delay. The output of the HPM is a function of voltage level and the HPM clock. As
shown in
Figure 2.5-1 , the HPM is embedded in the ARM Core voltage domain that is AVS controlled. It receives
the clock from the CMU, and outputs are connected to the APC1. It translates voltage level into system delay
information. The system delay information is then used by the APC1 to determine the optimum voltage level for
the target performance requirement.
To be short, the CMU supplies the target frequency required by the IEM software for that voltage domain, and the
HPM informs the APC1 when this target frequency is detected.
The HPM design is structurally coded in the synthesizable RTL to facilitate ease of place and route. This is
required to optimize the accuracy of the system delay tracking.
The HPM features are as follows:
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configurable for a different target frequency
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low power consumption overhead
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low area overhead
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DFT-ready for SCAN based ATPG