Samsung S5PC100, Руководство пользователя

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DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.1-38
4.2.18 Memory Chip1 Status Register (Chip1Status, R, Address=0xE600_004C)
CHIP1STATUS Bit Description R/W
Reset
Value
bank7_state [31:28] The current state of bank 7 of SDRAM chip1 R 0x0
bank6_state [27:24] The current state of bank 6 of SDRAM chip1 R 0x0
bank5_state [23:20] The current state of bank 5 of SDRAM chip1 R 0x0
bank4_state [19:16] The current state of bank 4 of SDRAM chip1 R 0x0
bank3_state [15:12]
The current state of bank 3 of SDRAM chip1
R 0x0
bank2_state [11:8] The current state of bank 2 of SDRAM chip1 R 0x0
bank1_state [7:4] The current state of bank 1 of SDRAM chip1 R 0x0
bank0_state [3:0]
The current state of bank 0 of SDRAM chip1
0x0 = Idle (precharged),
0x1 = MRS/EMRS,
0x2 = Deep power down,
0x3 = Self refresh,
0x4 = Auto refresh,
0x5 = Precharge power down,
0x6 = Row active,
0x7 = Active power down,
0x8 = Write,
0x9 = Write with auto precharge,
0xA = Read,
0xB = Read with auto precharge,
0xC = Burst stop,
0xD = Precharging,
0xE = MRR,
0xF = Reserved
R 0x0