Samsung S5PC100, Руководство пользователя

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SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.12-54
NORINTSTS Bit Description Reset Value
STABUFRDRD
Y [5]
Buffer Read Ready
This status is set if the Buffer Read Enable changes from 0 to 1. Refer
to the Buffer Read Enable in the Present State register. (RW1C)
'1' = Ready to read buffer
'0' = Not ready to read buffer
0
STABUFWTR
DY [4]
Buffer Write Ready
This status is set if the Buffer Write Enable changes from 0 to 1. Refer
to the Buffer Write Enable in the Present State register. (RW1C)
'1' = Ready to write buffer
'0' = Not ready to write buffer
0
STAD
MAINT [3]
DMA Interrupt
This status is set if the Host Controller detects the Host SDMA Buffer
boundary during transfer. Refer to the Host SDMA Buffer Boundary in
the
Block Size register. Other DMA interrupt factors may be added in
the future.
In case of ADMA, by setting interrupt field in the descriptor table, Host
Controller generates this interrupt. If it is used for debugging. This
interrupt is not generated after the Transfer Complete. (RW1C)
'1' = Generates DMA Interrupt
'0' = No DMA Interrupt
0
STABLK
GAP [2]
Block Gap Event
If the Stop At Block Gap Request in the Block Gap Control register is
set, this bit is set if both read/ write transaction is stopped at a block
gap. If Stop At Block Gap Request is not set to 1, this bit is not set to 1.
(RW1C)
(1) In the case of a Read Transaction
This bit is set at the falling edge of the DAT Line Active Status (When
the transaction is stopped at SD Bus timing. The Read Wait must be
supported in order to use this function).
(2) Case of Write Transaction
This bit is set at the falling edge of Write Transfer Active Status (After
getting CRC status at SD Bus timing).
'1' = Transaction stopped at block gap
'0' = No Block Gap Event
0
STATRANCMP
LT [1] Transfer Complete
This bit is set if a read/ write transfer is complete.
(1) In the case of a Read Transaction
This bit is set at the falling edge of Read Transfer Active Status. There
are two cases in which this interrupt is generated. The first is if a data
transfer is complete as specified by data length (After the last data has
been read to the Host System). The second if data has stopped at the
block gap and complete the data transfer by setting the Stop At Block
Gap Request in the Block Gap Control register (After valid data has
been read to the Host System).
(2) In the case of a Write Transaction
This bit is set at the falling edge of the DAT Line Active Status. There
are two cases in which this interrupt is generated. The first if the last
0