Samsung S5PC100, Руководство пользователя

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MIPI DSIM S5PC100 USER’S MANUAL (REV1.0)
8.7-32
3.2.19 FIFO Memory AC Characteristic Register (DSIM_MEMACCHR, R/W, Address = 0xECB0_0x48 :
hidden)
DSIM_MEMACCHR Bit Description R/W Reset Value
Reserved [31:16] Reserved - -
PGEN_SD [15] Sub display FIFO memory power gating R/W 0
RETN_SD [14] Sub display FIFO memory Retention R/W 1
EMAB_SD [13:11] Sub display FIFO memory B port margin adjustment R/W 0
EMAA_SD [10:8] Sub display FIFO memory A port margin adjustment R/W 0
PGEN_MD [7] Main display FIFO memory power gating R/W 0
RETN_MD [6] Main display FIFO memory Retention R/W 1
EMAB_MD [5:3] Main display FIFO memory B port margin adjustment R/W 0
EMAA_MD [2:0] Main display FIFO memory A port margin adjustment R/W 0
3.2.20 PLL Control Register (DSIM_PLLCTRL, R/W, Address = 0xECB0_0x4C)
This register configures PLL control, D-PHY, clock range indication, etc.
DSIM_PLLCTRL Bit Description R/W Reset Value
Reserved [31:28] Should be 0 - -
FreqBand[3:0] [27:24] Bitclk frequency band indicator for D-PHY global
timing R/W 0
PllEn [23] Enables PLL R/W 0
Reserved [22:20] Should be 0 - -
PMS[19:1] [19:1] PLL PMS value R/W 0
DpDnSwap [0] Set DpDnSwap signal connected to D-PHY module
input signal to swap Dp and Dn channel of D-phy. R/W 0
3.2.21 PLL Timer Register (DSIM_PLLTMR, R/W, Address = 0xECB0_0x50)
DSIM_PLLTMR Bit Description R/W Reset Value
PllTimer [31:0] PLL Timer for stability of the generated clock
(System clock cycle base)
If timer value goes to 0x00000000, clock stable bit of
status and interrupt register is set.
R/W 0xFFFFFFFF
3.2.22 DSIM IP Version Register (DSIM_VERINFO, R, Address = 0xECB0_0x7C)
DSIM_VERINFO Bit Description R/W Reset Value
VerInform [31:0] MIPI DSIM IP version information R 0