Samsung S5PC100, Руководство пользователя

Страница: 896 / 1863

S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG
8.10-53
8.2.29 Host Channel-n interrupt Register (HCINTn, R/W, Address = 0xEDn*20h)
Channel_number : 0
≤
n
≤
15
This register indicates the status of a channel with respect to USB- and AHB-related events. The application must
read this register if the Host Channels Interrupt bit of the Core Interrupt register is set. Before the application
reads this register, it must first read the Host All Channels Interrupt register to get the exact channel number for
the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the HAINT and GINTSTS registers.
HCINTn Bit Description R/W Reset Value
Reserved [31:11] - 21'h0
DataTglErr [10] Data Toggle Error R_SS_WC 1'b0
FrmOvrun [9] Frame Overrun R_SS_WC 1'b0
BblErr [8] Babble Error R_SS_WC 1'b0
XactErr [7] Transaction Error R_SS_WC 1'b0
NYET [6] NYET Response Received Interrupt R_SS_WC 1'b0
ACK [5] ACK Response Received Interrupt R_SS_WC 1'b0
NAK [4] NAK Response Received Interrupt R_SS_WC 1'b0
STALL [3] STALL Response Received Interrupt R_SS_WC 1'b0
AHBErr [2] AHB Error
This is generated only in Internal DMA mode if there is
an AHB error during AHB read/ writes. The application
reads the corresponding channel's DMA address
register to get the error address. R_SS_WC 1'b0
ChHltd [1] Channel Halted
Indicates the incomplete transfer either because of any
USB transaction error or in response to disable request
by the application. R_SS_WC 1'b0
XferCompl [0] Transfer Completed
Transfer completed normally without any errors. R_SS_WC 1'b0