Samsung S5PC100, Руководство пользователя

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CCAN S5PC100 USER’S MANUAL (REV1.0)
8. 5-16
6.2 DETAILED DESCRIPTION
These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and
the configuration of the CAN bit timing and provide status information.
6.2.1 CAN Control Register
•
CAN0_CON, R/W, Address = 0xEC70_0000
•
CAN1_CON, R/W, Address = 0xEC80_0000
CANn_CON Bit Description R/W Reset
Value
Reserved [15:8] Reserved R 0
Test [7] Test Mode Enable
1 = Test Mode
0 = Normal Operation
R/W 0
CCE [6] Configuration Change Enable
1 = The CPU has write access to the Bit Timing Register
(while Init = 1'b1)
0 = The CPU has no write access to the Bit Timing Register
R/W 0
DAR [5] Disable Automatic Retransmission
1 = Disables Automatic Retransmission
0 = Enables Automatic Retransmission of disturbed messages
R/W 0
Reserved [4] Reserved R 0
EIE [3] Error Interrupt Enable
1 = Enabled
−
A change in the bits BOff or EWarn in the Status
Register will generate an interrupt
0 = Disabled
−
No Error Status Interrupt is generated
R/W 0
SIE [2] Status Change Interrupt Enable
1= Enabled
−
An interrupt is generated if a message transfer is
successfully completed or a CAN bus error is detected
0 = Disabled
−
No Status Change Interrupt is generated
R/W 0
IE [1] Module Interrupt Enable
1 = Enabled
−
Interrupts sets IRQ_B to LOW. IRQ_B remains
LOW until all pending interrupts are processed
0 = Disabled
−
Module Interrupt IRQ_B is always HIGH
R/W 0
Init [0] Initialization
1 = Initialization is started
0 = Normal Operation
R/W 1
NOTE : The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or resetting Init. If
the device goes busoff, it sets Init of its own accord, stopping all bus activities. Once Init has been cleared by the
CPU, the device waits for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal
operations. At the end of the busoff recovery sequence, the Error Management Counters will be reset.