Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) USB2.0 HS OTG
8.10-33
GINTSTS Bit Description R/W Reset
Value
GOUTNak
Eff [7] Global OUT NAK Effective
Indicates that the Set Global OUT NAK bit in the Device Control
register (DCTL.SGOUTNak), set by the application, has taken
effect in the core. This bit is cleared by writing the Clear Global
OUT NAK bit in the Device Control register. R 1'b0
GINNakEff [6] Global IN Non-Periodic NAK Effective
Indicates that the Set Global Non-Periodic IN NAK bit in the
Device Control register (DCTL.SGNPInNak), set by the
application, has taken effect in the core. That is, the core has
sampled the Global IN NAK bit set by the application. This bit is
cleared by clearing the Clear Global Non-Periodic IN NAK bit set
by the application. This bit is cleared by clearing the Clear Global
Non-Periodic IN NAK bit in the Device Control register
(DCTL.CGNPInNak). This interrupt does not necessarily mean
that a NAK handshake is sent out on the USB. The STALL bit
takes precedence over the NAK bit. R 1'b0
NPTxFEmp [5] Non-Periodic TxFIFO Empty
This interrupt is asserted if the Non-Periodic TxFIFO is either half
or completely empty, and there is space for at least one entry to
be written to the Non-Periodic Transmit Request Queue. The half
or completely empty status is determined by the Non-Periodic
TxFIFO Empty Level bit in the Core AHB Configuration register
(GAHBCFG.NPTxFEmpLvl).
R 1'b1
RxFLvl [4] RxFIFO Non-Empty
Indicates that there is at least one packet pending to be read from
the RxFIFO. R 1'b0
Sof [3] Start of (micro) Frame
In Host mode, the core sets this bit to indicate that an SOF (FS),
micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB.
The application must write a 1 to this bit to clear the interrupt. In
Device mode, in the core sets this bit to indicate that an SOF
token has been received on the USB. The application reads the
Device Status register to get the current (micro) frame number.
This interrupt is seen if the core is operating at either HS or FS. R_SS
_WC
1'b0
OTGInt [2] OTG Interrupt
The core sets this bit to indicate an OTG protocol event. The
application must read the OTG Interrupt Status (GOTGINT)
register to determine the exact event that caused this interrupt.
The application must clear the appropriate status bit in the
GOTGINT register to clear this bit. R 1'b0
ModeMis [1] Mode Mismatch Interrupt
The core sets this bit if the application is trying to access:
•
A Host mode register, if the core is operating in Device mode
•
A Device mode register, if the core is operating in Host mode
R_SS
_WC
1'b0