Samsung S5PC100, Руководство пользователя

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CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
2.3-6
4 PLL
For PLL’s, the following three types are used:
•
pll6522x for APLL
•
pll6545a for MPLL
•
pll6545a for EPLL
•
pll6545a for HPLL
Above listed PLL’s is integer PLLs.
APLL is especially for D0 clock domain, which has ARM. It can make 50MHz ~ 2GHz, 45:55 duty frequency.
MPLL is especially for D1 clock domain. It supplies clock, 10MHz ~ 600MHz and 40:60 duty, to D1 bus and some
peripherals like SPI, HSMMC and etc.
EPLL is mainly used to generate audio clock.
HPLL is mainly used to generate HDMI clock, 74.176MHz and 74.25MHz.
4.1 EXAMPLE PLL PMS VALUE FOR PLL6522X (APLL)
Table 2.3-1. APLL PMS Value
FIN(MHz) Target FOUT(MHz) P M S VCOOUT FOUT(MHz)
12 133 3 266 3 1064 133.00
12 267 3 267 2 1068 267.00
12 400 3 400 2 1600 400.00
12 533 4 355 1 1065 532.50
12 667 3 333 1 1332 666.00
12 800 3 400 1 1600 800.00
12 933 4 622 1 1866 933.00
12 1066 3 267 0 1068 1068.00
12 1200 3 300 0 1200 1200.00
12 1333 4 445 0 1335 1335.00
133 MHz
12 1600 3 400 0 1600 1600.00
12 167 3 334 3 1336 167.00
12 333 4 444 2 1332 333.00
12 500 3 500 2 2000 500.00
12 666 3 333 1 1332 666.00
12 833 3 417 1 1668 834.00
12 1000 3 500 1 2000 1000.00
12 1166 4 389 0 1167 1167.00
12 1333 4 445 0 1335 1335.00
166 MHz
12 1666 3 417 0 1668 1668.00