Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER
5.3-11
2.6 WATCHDOG TIMER
The watchdog state machine monitors the various state machines of the controller. If the watchdog state machine
detects a potential hang in the controller or is waiting for some information from the OneNAND Flash memory
device, it is send out a watchdog interrupt if the watchdog timer expires. This does not trigger a state machine
change, and the OneNAND Flash memory device does not reset; software is expected to handle this condition
and take the necessary action. The software changes the watchdog reset values by writing to the
WTCHDG_RST_L and/or WTCHDG_RST_H registers.
2.7 ERROR HANDLING
If an error is detected, the controller updates the int_error_status register with the corresponding error information
and sends out an interrupt. In addition, the ERR_PAGE_ADDR and ERR_PAGE_ADDR_1 registers are updated
with the chip number, die number, block address and page address relating to the error situation. These registers
holds this information until they are read and the host clears the error bit in the
int_error_status register.
If an error is detected in a pipelined operation, only the error information is updated and an interrupt is sent. The
operation will not halt and continues until the operation is complete. Similarly, the error information is held until the
error bit in the
int_error_status register is cleared.