Samsung S5PC100, Руководство пользователя

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SPI CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.3-2
2.1 OPERATION
The SPI transfers 1-bit serial data between S5PC100x and external device. The SPI in S5PC100x supports the
CPU or DMA to transmit or receive FIFOs separately and to transfer data in both directions simultaneously. SPI
has 2 channels, TX channel and RX channel. TX channel has the path from Tx FIFO to external device. RX
channel has the path from external device to RX FIFO.
CPU (or DMA) must write data on the register SPI_TX_DATA, to write data in FIFO. Data on the register are
automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU (or DMA) must access the register
SPI_RX_DATA and data are automatically sent to the register SPI_RX_DATA.
2.1.1 Operation Mode
HS_SPI has 2 modes, master and slave mode. In master mode, HS_SPICLK is generated and transmitted to
external device. XspiCS#, which is the signal to select slave, indicates data valid when it is low level. XspiCS#
must be set low before packets are transmitted or received.
2.1.2 FIFO Access
The SPI in S5PC100x supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA
access to FIFOs are selected from 8-bit, 16-bit, or 32-bit data. If 8-bit data size is selected, valid bits are from 0 bit
to 7 bit. CPU accesses are normally on and off by trigger threshold. This is user defined. The trigger level of each
FIFO is set from 0byte to 64bytes. TxDMAOn or RxDMAOn bit of SPI_MODE_CFG register must be set to use
DMA access. DMA access supports single transfer and 4-burst transfer. In TX FIFO, DMA request signal is high
until that FIFO is full. In RX FIFO, DMA request signal is high if FIFO is not empty.
2.1.3 Trailing Bytes in the Rx FIFO
If the number of samples in Rx FIFO is less than threshold value in INT mode or DMA 4 burst mode and no
additional data is received, the remaining bytes are called trailing bytes. To remove these bytes in RX FIFO,
internal timer and interrupt signal are used. The value of internal timer is set up to 1024 clocks based on APB
BUS clock. When timer value is to be zero, interrupt signal is occurred and CPU can remove trailing bytes in
FIFO.