Samsung S5PC100, Руководство пользователя

Страница: 350 / 1863

ASYNC BRIDGE S5PC100 USER’S MANUAL (REV1.0)
3.4-8
2 THE PERFORMANCE IMPROVEMENT OF ASYNC BRIDGE IN S5PC100
2.1 LATENCY REDUCTION
The most outstanding architecture of S5PC100 is asynchronous clock scheme between D0 domain and D1
domain as shown in Figure 3.4-6. D0 domain is composed of high-speed memory system and the CPU system,
while D1 domain is composed of multimedia systems including MFC, LCD, Camera interface and TV system
whose performance largely depends on memory bandwidth.
D1 domain
D0 domain
Multimedia system
(MFC, 3D engine, LCD controller, Camera interface, TV system, and
etc.,)
Memory system
(DDR, SRAM, iROM, NF, and etc.,)
CPU system
(CPU, DMA, interrupt
controller, and etc.,)
Async
bridge
Default clock :
166MHz
Default clock :
133MHz
Figure 3.4-6 Simplified S5PC100 System bus Structure Focused on Clock
Although, the most masters of D1 domain’s performance depend not on memory latency but on memory
bandwidth, the 3D engine has cache interface whose performance is affected by memory latency. The MFC has
limited ability of hiding memory latency. Therefore, the less latency Async Bridge yields, the better performance
D1 domain can be obtained.
S5PC100 improved general asynchronous bridge scheme by adding path which has 1/2 clock cycle synchronizer
as shown in Figure 3.4-7.
When the meta-stability is removed in 1/2 cycle, you can program Async Bridge to use 1/2 cycle synchronizer,
otherwise, Async Bridge uses 1 cycle synchronizer as default. The change of synchronizer path can be executed
without stopping the Async Bridge operation.
In case of 1 cycle synchronizer, the Async Bridge penalty is 2.5 cycle at master domain clock + 2.5 cycle at slave
domain clock. By applying 1/2 cycle synchronizer, the Async Bridge penalty can be reduced by 0.5 cycle at each
clock domain.