Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) I2S CONTROLLER(5.1CH)
10.2-3
Figure 10.2-2 & Figure 10.2-3 shows the route of the root clock with internal master or external master mode
setting in I2S clock control block and system controller. Note that RCLK indicates root clock and this clock is
supplied to external I2S CODEC chip at internal master mode. To configure I2S V5.0 to work properly, refer
CLK_GATE_D2_0 in Clock Controller manual.
NOTE: CLK_GATE_D2_0[1:0] should be set to 2’b11.
Figure 10.2-2 S5PC100x Audio_CMU
Figure 10.2-3 I2S Clock Control Block Diagram
4.1.1 External DMA Transfer
To transfer up to 5.1 channel primary sound from s/w mixer to I2S, external DMA or SFR interface are used. To
play primary sound for 5.1 channels or record 2 channel sound, I2S has TXFIFO0, TXFIFO1, TXFIFO2,
TXFIFO_S and RXFIFO. I2S mixes primary sound in TXFIFO0 and secondary sound in TXFIFO_S and output
mixed sound stream to external codec logic.
In the external DMA transfer mode, the transmitter or receiver FIFO are accessible by external DMA controller.
DMA service request is activated internally by the transmitter or receiver FIFO state. The FTXEMPT, FRXEMPT,
FTXFULL, and FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state.
Especially, FTXEMPT and FRXFULL bit are the ready flag for DMA service request; the transmit DMA service
request is activated if TXFIFO is not empty and the receiver DMA service request is activated if RXFIFO is not full.
The external DMA transfer uses only handshaking method for single data. Note that during external DMA
acknowledge activation, the data read or write operation should be performed.
* Reference: DMA request point
- TX mode: (FIFO is not full) and (TXDMACTIVE is active)
- RX mode: (FIFO is not empty) and (RXDMACTIVE is active)